# How are conflicts between voltage sources or signals resolved?

I am trying to understand what happens when 2 supplies or voltage signals are tied to together as I come across similar situations where a Totem-pole output is also being pulled-up by a weak pull-up. In these cases I am wondering if the signal would conflict and result in an unknown final voltage level. Also, wouldn't the voltage difference between the signals cause unwanted current to flow between them which could be undesirable?

I did a simple simulation in LTSpice where I have 2 DC voltage sources connect in parallel across a load. On the right side are the current measurement results. The simulation result showed that the voltage across the load is 1.8v. On checking the current in the simulator, I observe that DC supply V1 provides the 0.18mA to the load, but DC supply V2 doesn't. I am wondering - how does the simulator decide which voltage sources provides the 0.18mA to the load (in this case V1 is providing 0.18mA and V2 is 0mA)? Also, shouldn't the current be provided equally by both supplies (V1 providing 0.09mA and V2 providing 0.09mA)?

Thanks for any help in developing a better understanding.

• Have you studied potential dividers yet? – Ignacio Vazquez-Abrams Dec 23 '15 at 6:27
• I know what a voltage divider is, but that wasn't exactly my question :(. A voltage divider from my understanding has a Vout and Vin. However, in my question, I have 2 Vins (Voltage inputs V1 and V2). Thanks – Joel Fernandes Dec 23 '15 at 6:36
• But it is exactly your answer. – Ignacio Vazquez-Abrams Dec 23 '15 at 6:37
• Ok, I will look into the topic of voltage dividers a bit more if you think it may help. But I am still not following, how the circuit I drew above is similar to a voltage divider (in which way). A voltage divider has 1 input and 1 output. Where as in the circuit I shared above, there are 2 input voltage sources driving the same line. Thanks – Joel Fernandes Dec 23 '15 at 6:42
• Look into the topic of source impedance -- an ideal voltage source (as in your simulation) always outputs a constant voltage, no matter how much current flows. This is just a heuristic for modeling, an ideal voltage source actually violates the principle of conservation of energy and is physically impossible. A practical voltage source like a battery, is equivalent to an ideal voltage source with a resistor in series, representing some equivalent internal resistance. So as more current is drawn, the voltage at the terminals can be less than the ideal voltage source voltage. – MarkU Dec 23 '15 at 6:50

This is an overdetermined circuit [that happens to have solution] so SPICE ignores one of the sources for the purpose of determining the currents. Try changing one source to 1.9V, see what happens. To spare you the suspense: In real life you have no such thing because all sources have internal resistance.

Also, judging by the fonts, it looks like you're using the Mac version of LTspice. With the PC version (4.23h), I can't reproduce your result; even with the same voltage on both sources I get the above message/dialog.

Ngspice also fail to solve this: http://www.ngspice.com/index.php?public_circuit=vv3bjo If you actually set Rser to 1 ohm on both of them (instead of just on one), then they do split the load current evenly between them. And if you redraw the "mystery" circuit above with an external resistor... ... then it's totally obvious that both ends of R2 are exactly at the same potential, so you get 0 current through it, and so 0 current though the source that has a Rser, as long as the other source doesn't have one.

• Actually, on Mac I get an error only if both of the sources has no internal resistance regardless of their voltage levels. If one of the has some internal resistance, the error goes away. – Joel Fernandes Dec 23 '15 at 7:10
• @JoelFernandes: Sure it does. But you're not showing the internal resistance in your circuit. What did you set it to? – Fizz Dec 23 '15 at 7:10
• Hi, I had set one to 1 ohm and the other to 0. That explains why all the current was flowing through the one without Rser as the current flows through least path of resistance.. but when I set them to the same internal res (I tried 1k ohm), then the current split equally between them as you said - so that makes sense. However - I am still trying to apply Ignacio's voltage divider suggestion and am not able to get a final voltage result on paper. Now my circuit has a V1 and V2 source of 1k resistance. The final voltage in SPICE is slightly lower at 1.714V and the current draw is 85.7uA – Joel Fernandes Dec 23 '15 at 7:34
• @JoelFernandes: It's not a voltage divider but a current divider. Also SPICE only calculates up to some decimal points. – Fizz Dec 23 '15 at 7:35
• The only way I arrive at a solution on paper, is I treat both the voltage sources as a combined voltage source with a combined internal resistance of half of 1k, that's 500 ohm. Then applying the voltage divider concept, I arrive at 1.714V. The 1.8V supplies goes through 500 ohm and then 10K of the load, so its 1.714V before the load. – Joel Fernandes Dec 23 '15 at 7:38

A voltage divider has 1 input and 1 output.

Incorrect.

The classic schematic of a potential divider we have the input voltage at the top, a resistor connecting it to the output voltage, and a further resistor connecting to ground. But the thing is that ground is also a voltage. And there is no requirement for the second voltage to be ground.

So instead of subtracting 0V, dividing, and then adding 0V as we do with a ground-referenced potential divider, we subtract the second voltage, divide, and then add the second voltage, with a ground-referenced divider simply being the degenerate case of subtracting and then adding 0V.

• I added a comment to the answer above regarding using the "0V" as a second voltage source and tried to apply the potential divider concept. Do take a look at my comment if you get a chance, thanks. – Joel Fernandes Dec 23 '15 at 8:00
• @JoelFernandes: (Z2/(Z1 + Z2))(V1 - V2) + V2, just as my answer describes. – Ignacio Vazquez-Abrams Dec 23 '15 at 8:03