# JTAG TAP Design code verilog( Advanced Debug Interface)

I am designing a JTAG unit for a processor. For that, i have initially designed a TAP controller by looking at the FSM of the TAP. Now, i have being given this snippet of code:

reg [IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [IR_LENGTH-1:0]  latched_jtag_ir;   // latched_jtag_ir_neg;
wire instruction_tdo;

begin
jtag_ir[IR_LENGTH-1:0] <= IR_LENGTH'b0;
else if (test_logic_reset == 1)
jtag_ir[IR_LENGTH-1:0] <= IR_LENGTH'b0;
else if(capture_ir)
jtag_ir <= 4'b0101;          // This value is fixed for easier fault detection
else if(shift_ir)
jtag_ir[IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[IR_LENGTH-1:1]};
end

assign instruction_tdo = jtag_ir[0];  // This is latched on a negative TCK edge after the output MUX

// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (posedge s_clk_neg or negedge trstn_pad_i)
begin
latched_jtag_ir <= IDCODE;   // IDCODE selected after reset
else if (test_logic_reset)
latched_jtag_ir <= IDCODE;   // IDCODE selected after reset
else if(update_ir)
latched_jtag_ir <= jtag_ir;
end


s_clk is the inverted clock

I am not able to understand this part of the code.Firstly, the comments at various points read that the data needs to be latched at the negative edge of the cycle. I am not able to understand how is the assign statement doing it ? Also,why has he used 2 ir- 1)JTAG_ir 2)latched_jtag_ir.

I have gone through various modules.All of them say that the IR contains some cells and needs to be designed according to IEEE standard 1159.4. Could some tell me what is the purpose of the two registers?