# JTAG TAP Design code verilog( Advanced Debug Interface)

I am designing a JTAG unit for a processor. For that, i have initially designed a TAP controller by looking at the FSM of the TAP. Now, i have being given this snippet of code:

reg [IR_LENGTH-1:0]  jtag_ir;          // Instruction register
reg [IR_LENGTH-1:0]  latched_jtag_ir;   // latched_jtag_ir_neg;
wire instruction_tdo;

begin
jtag_ir[IR_LENGTH-1:0] <= IR_LENGTH'b0;
else if (test_logic_reset == 1)
jtag_ir[IR_LENGTH-1:0] <= IR_LENGTH'b0;
else if(capture_ir)
jtag_ir <= 4'b0101;          // This value is fixed for easier fault detection
else if(shift_ir)
jtag_ir[IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[IR_LENGTH-1:1]};
end

assign instruction_tdo = jtag_ir[0];  // This is latched on a negative TCK edge after the output MUX

// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (posedge s_clk_neg or negedge trstn_pad_i)
begin
latched_jtag_ir <= IDCODE;   // IDCODE selected after reset
else if (test_logic_reset)
latched_jtag_ir <= IDCODE;   // IDCODE selected after reset
else if(update_ir)
latched_jtag_ir <= jtag_ir;
end


s_clk is the inverted clock

I am not able to understand this part of the code.Firstly, the comments at various points read that the data needs to be latched at the negative edge of the cycle. I am not able to understand how is the assign statement doing it ? Also,why has he used 2 ir- 1)JTAG_ir 2)latched_jtag_ir.

I have gone through various modules.All of them say that the IR contains some cells and needs to be designed according to IEEE standard 1159.4. Could some tell me what is the purpose of the two registers?

On the rising edge, sample TMS, TDI. On the falling edge, TDO changes state. Additionally, by spec, when TDO is inactive, it should be High-Z.

So as you probably know, you enter a state on the rising edge of TCK. You may then perform an action as soon as the next falling edge, or the next rising edge (if you are still in the state). For your logic, your device should only consider the instruction 'latched' upon the completion of Update-IR. Section 6.2.1, Rule d) indicates that you shall latch the data from the register at the falling edge of TCK in the Update-IR state.

Now, as to why he used two registers, remember the structure of JTAG registers. During the Shift-xR phase, you're shifting through data for the entire chain. If you have a device with a 8-bit IR that is second in the chain, the entire chain length is actually 9 bits (assuming the first device is in BYPASS). Upon shifting in the correct number of bits, you then latch (I guess you could consider it a 'copy') the desired instruction into your internal state register.

My strong recommendation: if this is destined for production or silicon, purchase a qualified / validated JTAG TAP IP. Additionally, get access to the published specification. It takes some time to understand the nuances of the protocol, and a faulty JTAG implementation is the last thing you want in a production device.