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I have implemented the following with TTL 74LS chips:

  1. A NE555-based timer generates a clock signal every second
  2. The clock signal is fed into a TTL 7493 4-bit binary ripple counter.
  3. The 4-bit binary counter value is fed into a 4-to-16 decoder that I have built from TTL 7408 and TTL 7404 gates.

When I connect the timer and only the 4-bit ripple counter, the ripple counter outputs the correct binary value. When I use the 4-to-16 decoder with a hand-coded binary value, it also produces the high-signal on the correct output line.

But as soon as I feed the output from the 4-bit ripple counter into the 4-to-16 decoder, the ripple counter produces an incorrect binary counting sequence. I'm already struggling with this problem over a few days, and I have no idea how to troubleshoot it nor I have no idea why this behavior happens.

As I have said, the 4-to-16 decoder and the 4-bit ripple counter are working perfectly when I use them on their own, but as soon as I chain them up, the strange behavior occurs.

Every help and tip is appreciated :-)

Thanks & nice greetings,

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    \$\begingroup\$ The devil is in the detail so show the circuit and make sure you have used enough power decoupling capacitors, your power supply is rated for all the load and you have no bread board nuances (if you have used BB). \$\endgroup\$
    – Andy aka
    Commented Dec 23, 2015 at 16:37
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    \$\begingroup\$ Please provide a schematic of at least part of your decoder. My guess is that you are exceeding the fanout of the 7493. Standard 7400 drive specs are a maximum of 20 inputs per output. How many gates are your decoder inputs? \$\endgroup\$ Commented Dec 23, 2015 at 16:53
  • \$\begingroup\$ Currently I don't use any decoupling capacitor. Can it make a difference if I add a 0.1uF at every TTL IC that I use in the circuit? \$\endgroup\$ Commented Dec 23, 2015 at 16:53
  • \$\begingroup\$ The decoder uses 16 AND and 1 NOT gate. \$\endgroup\$ Commented Dec 23, 2015 at 16:54
  • \$\begingroup\$ @KlausAschenbrenner - Well, there's your problem. A 4 to 16 decoder made with 7408s and 7404s (assuming all 16 outputs are produced) will require more than 16 AND gates. So you've done something wrong in your decoder design. And one more time - show us a schematic! \$\endgroup\$ Commented Dec 23, 2015 at 17:50

2 Answers 2

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The output of a ripple counter does not change from one 'count' to another instantaneously. The new state 'ripples' across the outputs until it has reached the new state.

It is possible that these 'in between' states show up on the outputs of the 4 to 16 decoder as 'random' outputs.

If you clock the ripple counter manually and then look at the outputs they will be correct, because the ripple happens quickly, but the 4 to 16 decoder is fast enough to change according to the in between results.

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  • \$\begingroup\$ Hello, The 555 timer runs on a clock cycle of 1Hz, so it's easy to follow the output of the ripple counter. And I don't get any "in-between" results from the ripple counter. The other interesting thing is that everything works as expected when I attach a 3/8 decoder to the output of the ripple counter... Thanks, -Klaus \$\endgroup\$ Commented Dec 23, 2015 at 20:48
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If you're using 2 input ANDs for the decode, you'll need 32 of them in the second rank to decode the minterms and then you'll need 16 more in the third rank to reduce the 32 output states from the front rank to 16 one-hots. That's 48 gates, so you're right about that. All that's left, then, if your decoder worked perfectly when you excited it, is to figure out why it doesn't work when it's driven by the counter. My guess would be that not buffering the counter's outputs would load its outputs to the point where they'd fall short of being a 1 or a 0 as far as the decoder was concerned.

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  • \$\begingroup\$ Thanks for your answer. How can I make sure to buffer the outputs from the counter? \$\endgroup\$ Commented Dec 23, 2015 at 20:00

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