I have to do the things ICs in the SE/NE560 series do with PIC18F4550. I mean I will provide two input signals with different frequencies and this two input will be synchronized. This is what we want to achieve. Any helps or thoughts will be appreciated.

For example two AC signals with different frequencies like 50Hz , 100 Hz. I want to force 50Hz signal to rise up 100Hz.

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    \$\begingroup\$ It's really unlear what you are trying to do. Clearly you need a PLL but you haven't explained what signals they are and what you are hoping to achieve. \$\endgroup\$ – Andy aka Dec 23 '15 at 17:41
  • \$\begingroup\$ @Andyaka I do not have any spesific signal in my mind. It can be any of them. I just want to do what IC 565 or others does with PIC18F4550. I want learn the logic about how it should be done. \$\endgroup\$ – Pyro Dec 23 '15 at 18:22
  • \$\begingroup\$ A 565 doesn't need a PIC and a PIC doesn't need a 565. Both can be explained independently. Trying to conjure an idea in my mind about how the two can work together to produce the functionality of "something that only you seem to know about" is beyond the scope of my telepathic powers. \$\endgroup\$ – Andy aka Dec 23 '15 at 18:24
  • \$\begingroup\$ @Andyaka I did not mean both PIC and the IC will work together. I will try to do what IC565 does with a PIC18F4550. \$\endgroup\$ – Pyro Dec 23 '15 at 18:27
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    \$\begingroup\$ "For example two AC signals with different frequencies like 50Hz , 100 Hz. I want to force 50Hz signal to rise up 100Hz." This doesn't explain what you want (a 50Hz signal is 50Hz - 'rise it up' to 100Hz and it isn't 50Hz!). What do you actually want to do:- double the input frequency, lock an oscillator to a multiple of another frequency, or simulate an NE560 in firmware with a PIC? \$\endgroup\$ – Bruce Abbott Dec 23 '15 at 18:48

You begin with a voltage controlled oscillator (VCO). Here's one that might be tunable between 600 MHz and 700 MHz: -


And let's say you want it to be exactly 640 MHz.

What you can do is divide down the output frequency using digital dividers like this: -

enter image description here

Each stage can reduce the output frequency of the VCO by 2 so, you string (say) 6 of these stages together to divide the nominal 640 MHz down by 64 to a nominal value of 10 MHz.

Then you have a crystal controlled oscillator running at exactly 10 MHz and you use some digital logic circuits to compare this exact 10 MHz with the nominally 10 MHz signal you have made from the output of the VCO.

It's a called a frequency phase detector: -

enter image description here

Refclk is the precise 10 MHz clock and fbclock is the divided down frequency from your VCO. This circuit produces two lots of pulses, up and down and these can be fed (via transistors) into a low pass analogue filter and analogue amplifier to produce a control signal.

That control signal then feeds the input of the VCO.

What theoretically happens next is a metric ton of math but the usually, the VCO is driven by the control signal to produce exactly 640 MHz - any error gets detected by the frequency phase detector and this produces a small change in the analogue signal that corrects the VCO.

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