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I'm new in Verilog and I need to create a module that when Entry=1, it will increment 5'b000100 in the "Money" output.

This is the code that I made, but it's not working properly. The program it's not storing the total of the money(that's what I want my program to do).

For example, Everytime a person enters a football stadium, she pays for the ticket, and my machine will store the total money gained. The maximum of people that can enter the stadium is 15 (thats why I used 6 bits, because 4*15=60)

My "machine" isn't storing the total earned.

My code

    module Machine_Money(Entry, Money);
         input Entry;
         output [5:0] Money;
         reg [5:0] Money;

            always@(Entry)

                begin
                Money = 6'b000000;
                    if (Entry)
                    Money = Money + 6'b000100;
                end
   endmodule

Thanks.

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        always@(Entry)
                begin
                Money = 6'b000000;
                    if (Entry)
                    Money = Money + 6'b000100;
                end

Whenever the Entry input changes, you set Money to 0, then maybe add 4. So Entry will always be either 0 or 4.

You might want to put the Money = 6'b0 line within an if (reset) or you might want to move it into an initial block or remove it altogeter, or whatever, depending what functionality you actually want.

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    \$\begingroup\$ Also note that using always@(Entry) like this is almsot certain to give wrong results in synthisis. If you want to trigger on a signal you need to use posedge or negedge. Finally as a general rule you should only trigger on dedicated clocks, not on artbitary signals. \$\endgroup\$ – Peter Green Dec 24 '15 at 6:03
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@ThePhoton's answer is correct as to one minor issue with your code that essentially makes the always block infer a multiplexer with 0 as one input and 4 as another input (with Entry being the select signal).

However, the think to remember is FPGA's like synchronous logic. Your code as it is written is completely asynchronous - there is no clocked logic. So assuming you made the corrections @ThePhoton suggested, it still won't work properly. While Entry is high the value of Money would rapidly count up at whatever the propagation delay of the circuit is. So unless your people are entering every few 100's of picoseconds, that isn't going to be meaningful. On top of that, each bit in the count may have a different delay meaning you will quickly end up with utter nonsense in your counter.

The correct way to do this is to add a clock to the circuit which essentially allows the value going into and coming out from the adder to be resynchronised meaning that each bit will have effectively the same delay as they will all be latched on the clock edge.

The code would be something like:

always @ (posedge clock) begin //-- New clock signal, we act on its rising edge
    if (reset) begin
        Money <= 6'd0; //-- Reset money when reset signal is high
    end else if (Entry) begin
        //-- Whenever Entry is high at a clock edge, we increment money
        Money <= Money + 6'd4; //-- Or 6'b000100;
    end
end

With this new code, you would need your Entry signal to be also synchronised to the clock in such a way that it is only high for one clock cycle whenever someone enters. If the clock was, say 20MHz, that would mean the signal is checked once every 50ns, which is far faster than anyone could ever enter, so the clock wouldn't affect your ability to count entries.


As a side not, I would also suggest you use the ANSI standard module declaration as it is much easier to keep track of what ports are what type. Your declaration is:

Machine_Money(Entry, Money);
         input Entry;
         output [5:0] Money;
         reg [5:0] Money;

Where the ANSI equivalent would be:

Machine_Money (
         input            Entry,
         output reg [5:0] Money
);

Notice how it is much cleaner and you don't need to duplicate the name of the Money port three times. Note that the names don't have to line up (I added lots of spaces so they do), I just find it looks cleaner.

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