I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing error. I have been using the standard 100 Mhz clock which comes with the board. I now think I need something slower like 50 Mhz. I don't think I can change the standard clock since that is fixed at 100 Mhz by the board so I think I need to create a generated clock. I added the following lines to my xdc file.
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports clk]
create_generated_clock -divide_by 2 -source [get_ports clk] [get_ports clk2]
I then get the error. Generated clock clk2 has not logical path from master clock sys_clk_pin. Am I missing a step. Do I need to do something more than create it in the XDC file? Here is the header for my top level module.
module serial_emitter(
output RsTx,
input RsRx,
input clk,
input clk2,
output [3:0] an,
output [6:0] seg);
I want the slower clock to map to the clk2 input.
create_generated_clock
instructions are nothing more than directives to the static timing analyser to describe what clocks are what. You actually need to implement the logic or primitives that produce the clock. \$\endgroup\$ – Tom Carpenter Dec 24 '15 at 15:06