# How many ground and power pins to have in a connector?

I'm designing a daughter board for a project. There are 35 I/O pins that need to go to the board. How do I determine the number of ground and power pins to include? How do I determine the placement of those pins throughout the connector?

I know something like this would be bad, as I was told:

P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
G G  IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO


I'm guessing something like this isn't much better:

P IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO G
G G  IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO P


The board is for a microprocessor, I'm going from a breadboard to a PCB and am trying to learn as I go :)

23 pins are address lines, 8 data lines and 4 signal lines (Read, Write, Chip Enabled and Direction). There is no clock line on this board but there might be on others I'll be making. The clock of the microprocessor will be 50MHz or less, down to <1MHz. The connector itself will be a standard .1" pins.

• What's the expected length of the harness and the IO specs of the processor (rise and fall time)? – Krunal Desai Dec 24 '15 at 18:40
• @KrunalDesai - To be honest I didn't expect all this to matter :) the rise/fall time is 5ns. I'm planning on this being a male header 2 rows of pins at .1" spacing to plug directly into a female header on the main board. Though I could see the benefit of a 2-3cm ribbon cable as well. – Justin808 Dec 24 '15 at 18:45
• More ground is better, but I have a Beaglebone Black project that runs at close to 50 MHz, with the pin pattern similar to your 1st diagram (0.1" headers) and it is entirely functional. Haven't tested EMC though. Many systems with this kind of data rate operate well with only limited number of ground pins. – The Photon Dec 24 '15 at 20:14
• Ah, this is board to board. Chances are with 5ns rise/fall times you will not have to worry about transmission line effects. Samtec makes some nice board-to-board connectors that have large solid blades for carrying power/ground, surrounded by signal pairs and pins. That would do you quite well. – Krunal Desai Dec 24 '15 at 22:19
• +! signal and gnds should be close .Power thinks it is ground if bypassing is good . – Autistic Dec 31 '15 at 21:16

There's a great book from Henry Ott that covers this -- unfortunately I'm on vacation so I can't take a picture of the relevant diagram. The book is Electromagnetic Compatibility Engineering.

Here's some quick points though:

• from a DC power point of view, how much current does your device require? Look at the rating of each conductor, de-rate if necessary to give yourself margin and choose accordingly the number of power pins. Remember you need 1:1 power to ground.
• from a AC POV, you want to minimize the loop return area of all of your signals. You want each signal to have its own GND / return immediately adjacent -- two schemes to do this:

S G G S G G S G G S G G S (one-two ground per signal, no adjacent signals)

G S S G S S G S S G S S G (one ground per signal still, more efficient utilization of space).

The idea is to minimize crosstalk and radiated emissions. While DC follows the path of least resistance, AC follows the path of least impedance. In this case, providing a return path immediately adjacent to a signal will help minimize the size of the overall current loop, reducing your radiated emissions.

Additionally, are these all single-ended? Differential? Expected signal rate? Expected edge rates?

• This is good advice. The faster your signal rate, the longer your cable, the bigger the boards, the more important it is to do it exactly like this. So if you have a board-to-board (no cable) interconnect, with low speed signals, you can cheat a bit. The other bit of advice I have is that you should consider if some signals are aggressor signals (such as clocks) or victim signals (analog signals which have high-impedance termination). You should keep aggressors away from victims in the pinout, and separated by GND. Good luck! – mkeith Dec 24 '15 at 18:25
• Your first pattern is 2 grounds per signal. One ground per signal would be GSGSGSGSGS. – WhatRoughBeast Dec 24 '15 at 18:29
• Oops, yes -- I will edit that to reflect what I actually meant which was no adjacent signals, at least one ground per signal. – Krunal Desai Dec 24 '15 at 18:29
• Its maybe beneficial to make clear whether this pattern should be followed on the connector or the cable. E.g. FFC cables will match connector 1:1; but ribbon cable connector signals are are interleaved per row. From my understanding, how the signal travels through the cable is important. – Hans Dec 24 '15 at 22:18
• Agreed -- I will update my answer with the relevant diagrams for FFC/ribbon cables. The intent though is for this scheme to match on the cable, e.g. on a ribbon cable, each signal wire will have at least one return wire adjacent to it. – Krunal Desai Dec 26 '15 at 22:41

For direct board-to-board connections, I generally figure that as long as each signal is adjacent to at least one ground (including diagonally), the loop area is minimized enough for good EMC performance. I usually end up with something like this on a 2-row connector:

S  S  S  S  S  S  S  S  S  S  S
G  S  G  S  G  S  G  S  G  S  G


or even:

S  S  S  G  S  S  S  G  S  S  S
S  G  S  S  S  G  S  S  S  G  S


Overall, either scheme is roughly three signals for each ground. Four your 35 I/O signals, I would have about 12 grounds, and use a 48 or 50 pin connector. Some of the grounds can be replaced with power pins as long as there is good decoupling between power and ground on both boards.

• Oh, I didn't think about diagonals -- that makes perfect sense. I'd be curious to quantify how well diagonals work but I'd buy that it delivers good EMC performance as well. – Krunal Desai Dec 25 '15 at 0:05