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Guys My doubt is that for the following cascode configuration how can the minimum voltage needed at the drain of M1 be Vt + 2 Vov for M1 and M2 to be in saturation ?? Vov is the over drive voltage whihc is Vgs- Vt.

For saturation considering that Vds > Vov. At transistor M1 the minimum voltage should be 2Vt + 2Vov in my opinion. But it is said that it is Vt + 2 Vov , how is this so ??

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  • \$\begingroup\$ What exactly is your question. Please add the question to your original post and not here in the comments. \$\endgroup\$ – Transistor Dec 24 '15 at 23:49
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    \$\begingroup\$ What is all that rubbish printed behind your picture - what is "EEL782" all about. Do yourself a favour and draw a proper circuit diagram. This shouldn't be difficult. \$\endgroup\$ – Andy aka Dec 25 '15 at 1:49
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With the gate of M1 held at 2VT+2OV (by M3 & M4), you need VT+OV at its source (a VGS lower, or VT+OV lower), so M1's drain needs to be OV higher, or a total of VT+2OV.

M2 doesn't have to be at Vt+OV -- it could be just OV, but then (with the bias you have), you couldn't keep M1 in saturation.

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  • \$\begingroup\$ Having OV at the drain of M2 would not keep even M2 at saturation. By the following at M2, Vds > Vgs-Vt; = Vd>Vg-Vt; =Vd >Vt+Vov-Vt; =Vd>Vov So by this Vd should minimum be above Vov to be in Saturation so if it is at Vov then it will not be at saturation, Is it not ?? \$\endgroup\$ – Bhuvanesh Narayanan Dec 25 '15 at 0:32
  • \$\begingroup\$ at the edge of saturation, for M2, you need VD >= Vov. \$\endgroup\$ – jp314 Dec 25 '15 at 1:09
  • \$\begingroup\$ Ahh sure now I get it ! And just need to be a little bit more clear. What made you say that " you need VT+OV at its source (a VGS lower, or VT+OV lower)" is there a logically intuitive reason to say this, because if I understand this clearly then I'd be pretty sure on this thing ! \$\endgroup\$ – Bhuvanesh Narayanan Dec 25 '15 at 1:34
  • \$\begingroup\$ M1's gate is fixed at 2VT+2OV. In saturation, at the 'correct' bias current, its VGS will be the same as the others - VT+OV. If its VGS was lower, then it couldn't run the current; if VGS is higher then either its is running more current (in saturation at the higher current), or it is not in saturation (e.g. you can put VGS=5 V on a FET, but if VDS is small, it is not in saturation). \$\endgroup\$ – jp314 Dec 25 '15 at 3:49

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