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Original Video [https://youtu.be/d3bF2v056WU?t=1m57s][1]

See pic: http://i.imgur.com/QgUIyE0.png

Questions about the timing diagram on the right:

  1. G looks like a ramp shape that goes down. Does that mean voltage was a higher constant then went down to a lower one?

  2. What are the boxes containing V1 and V2? If they are voltages why not just horizontal lines?

  3. What are these XXXXX's between those boxes containing V1 and V2?

I've been googling d latch timing diagrams to figure out the above- haven't found it yet but did notice that alot of other d latch timing diagrams look like horizontal lines/box/square wave shapes

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  • \$\begingroup\$ 'X' are intended to be 'don't cares'; you'll hear engineers refer to states they don't care about as 'X's \$\endgroup\$ – Krunal Desai Dec 25 '15 at 23:25
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  1. G is indeed a voltage that was at a higher level and then drops to a lower level. This is dependent on the logic level of the D-latch, for example if it is 5V logic then "high" or "1" is 5V and "low" or "0" is 0V. It's a ramp because voltage levels don't change instantaneously in the real world.

  2. The V1/V2 boxes are indeed voltage levels, however notice that they contain two horizontal lines rather than one like the G signal. This represents the fact you don't really care about the voltage levels, you just know they are some level for the latch to store. The cross between V1 and V2 represents transition between the two pulses; notice that when D transitions it is not immediately reflected on Q because of propagation delay, represented by Tpd.

  3. The XXXXX's basically says that with G being "low", whatever changes you make on D will not be reflected on Q; in other words Q is "latched" to V2.

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The boxes mean "it is a defined value" as binary. Timing diagrams are only about timing related aspects, and do not contain the truth table, therefore most values are only represented with regard to their validity, not their value.

The Gate signal is represented as binary though, because it´s value at its change (the falling flank) is important for the timing of the system. Note there is no "up" change shown for the Gate signal: it does not change the state of the system, and is irrelevant.

On an input signal, the Xs mean the input is not relevant in our diagram, meaning they don´t change the outputs.

On an output signal, it means the output is not defined, or not relevant to our problem.

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