I have a module to display a base 10 number on my 7-Segment display.
module displayN(input [13:0] n, input clk, input [3:0] an, input [6:0] seg); wire [3:0] d1 = n % 10; wire [3:0] d2 = (n / 10) % 10; wire [3:0] d3 = (n / 100) % 10; wire [3:0] d4 = (n / 1000) % 10; display4(d4, d3, d2, d1, clk, an, seg); endmodule
It takes in a 14 bit number and computes the digits and hands it off to another module which actually displays it.
Right now I am working on a program which uses a USB-UART connection and displays the value of the last byte sent on my 7-Seg. Here is my top level module.
module uart_top(input clk, input rx, output tx, output [3:0] an, output [6:0] seg); wire [63:0] count; wire [7:0] out; uart_receive r(clk, rx, count, out); reg [7:0] oreg; always @(out) oreg = out; displayN d4(oreg, clk, an, seg); ila_0 i(clk, rx, out); endmodule
This code is currently working. When the output of my uart receiver changes I copy the output to a register, and then send it to my display module. This seems to work correctly when I try it on my card. I am assuming that even though the module is expecting 14 bit it just fills 0 for the upper 14. However, when I try to pass "out" directly to the module like
displayN d4(oreg, clk, an, seg); I get some error about a black box. Why can I do this for a register but not a wire?
Here is the exact error message I get during synthesis.
[Project 1-486] Could not resolve non-primitive black box cell 'displayN' instantiated as 'd4' [/home/chase/vivado-workspace/UART/UART.srcs/sources_1/new/uart_top.v:37]
Also here is the uart_receive.
module uart_receive#(parameter BAUD_RATE = 9600, parameter CLOCK_SPEED_MHZ = 100) (input clk, input rx, output reg [63:0] read_count = 0, output reg [7:0] data); localparam SAMPLE_BAUD_RATE = BAUD_RATE * 8; reg reading = 0; reg [8:0] bit_stream = 0; reg [3:0] bit_index = 0; wire sample_tick; baud_gen#(SAMPLE_BAUD_RATE, CLOCK_SPEED_MHZ) s(clk,, sample_tick); wire baud_tick; baud_gen#(BAUD_RATE, CLOCK_SPEED_MHZ) b(clk, !reading, baud_tick); always @(posedge clk) begin if(sample_tick && !reading && !rx) begin reading <= 1; bit_index <= 0; end else if(baud_tick) begin bit_index <= bit_index + 1; bit_stream[bit_index] <= rx; if(bit_index == 8) begin reading <= 0; read_count <= read_count + 1; data <= bit_stream[7:0]; end end end endmodule
It seems to work if I remove the
ila_0 i(clk, rx, out); which is the Integrated Logic Analyser I was using for debugging. I always had out hooked directly up to it even when I was using the resister in displayN. I wonder why out could not be connected to both of them at a time.