Although forcing the clock select should work in theory, you could have a problem with synchronization in practice.
SPI does not have framing bits. Instead, the slave knows that that a transaction always starts at the first clock transition after it is selected.
In theory, if you tie the select line low, then the salve should be ready and waiting and the 1st bit you send will be the 1st bit it receives. As long as you guys stay in sync, everything should be hunky dory.
Unfortunately it might not always work. During power up, say, there can be times when the clock line is in an intermediate state and the slave could potentially see a clock pulse when the master didn't send one. If this happens, the master and the slave will forever be out of sync.
You might be able to mitigate the risk of this start-up problem by using a clock polarity with a base of 0 and by using a pull-down resistor large enough to ensure that the clock stays low during power up by not so large that you can not actively drive it high.