This is supposed to be a simple NAND gate. I understand how the output is 1 if one of the inputs is zero but if both inputs are 1 then the base of Q1 is supposed to be zero. This is what I don't understand. I know that Q2 and Q3 will be in cut off so the base of Q1 is floating. If that is true, how is it zero then?When A and B are open does current flow through Q2 Q3 via R1 to turn on Q1?
I've redrawn the schematic in a way that is easier for me to understand. Perhaps it will help others.
When A and B are high, everything to the left of Q1's base can only lead back to Vdd. There's no path to ground at all. And thanks to Ignacio for pointing out the current from base to collector at Q2 and Q3 -- I've been looking at these "equivalents" since 1973 and never really understood what they were doing.