The code bellow is to take the reciprocal of a fixed point number using Newton's method. When start is asserted the state machine enters the estimate state. To get a starting point, I start at 1/2^N where N is the index of the most significant bit. It seems to work fine in simulation but when I synthesize it I get the following warning:

[Synth 8-5413] Mix of synchronous and asynchronous control for register abs_n_reg in module qinv. ["/home/chase/vivado-workspace/FixedMath/FixedMath.srcs/sources_1/new/qinv.v":45]

I'm not really sure why I'm getting this or how to fix it. abs_n_reg is the absolute value of n. I'm only setting its value from one of my always blocks.

  module qinv(output reg signed [63:0] inv,
                output reg ready = 1'b1,
                input signed [63:0] n,
                input start,
                input clk);

        reg sign;
        reg [63:0] abs_n;

        reg [63:0] cur_inv;
        reg [63:0] next_inv;

        localparam READY = 2'b00,
                   COMPUTE = 2'b01,
                   ESTIMATE = 2'b10;

        reg [1:0] state = READY;
        reg [1:0] next_state = READY;

        wire [5:0] mb;
        msb m(abs_n, mb);

        always @(posedge clk or posedge start) begin
            if(start && state == READY) begin

                if(n[63] == 1'b1) begin
                    abs_n <= -n;
                    sign <= 1'b1;
                end else begin
                    abs_n <= n;
                    sign <= 1'b0;

                ready <= 1'b0;
                cur_inv <= 64'b0;
                state <= ESTIMATE;

            end else begin
                state <= next_state;
                cur_inv <= next_inv;

                if(state == COMPUTE && next_state == READY) begin
                    ready <= 1'b1;
                    if(sign) inv <= -next_inv;
                    else inv <= next_inv;

        wire [63:0] p1, p2;
        qmul m1(p1, abs_n, cur_inv);

        reg [63:0] diff;
        qmul m2(p2, diff, cur_inv);

        always @* begin
            next_inv = 0;
            next_state = READY;
            diff = 0;

            if(state == ESTIMATE) begin
                next_inv = {1'b1, 63'b0} >> mb;
                next_state = COMPUTE;
            end else if(state == COMPUTE) begin
                diff = {30'b0, 2'b10, 32'b0} - p1;
                next_inv = p2;
                if(next_inv[63:1] == cur_inv[63:1])
                    next_state = READY;
                    next_state = COMPUTE;


    module msb(input [63:0] n, output reg [5:0] m);
        integer i;
        always @* begin
            m = 0;
            for(i = 0; i <= 63; i = i + 1)
                if(n[i] == 1'b1) m = i; 


    module div_test();

        reg clk = 0;
        always #5 clk = ~clk;

        wire ready;
        wire [63:0] out;
        reg start = 0;
        reg [63:0] in = {8'd207, 24'b0};
        qinv d(out, ready, in, start, clk); 

        initial begin
            #5 start = 1;
            #10 start = 0;
            #1000 $finish;

1 Answer 1


It's exactly as the warning says, you are mixing synchronous logic with asynchronous logic.

You can not use ... or posedge start ....

  • \$\begingroup\$ I often see that with an async reset. I figured start would kind of do something similar. \$\endgroup\$
    – chasep255
    Dec 30, 2015 at 0:21
  • \$\begingroup\$ @chasep255 You should not use asynchronous resets on FPGAs, too :). \$\endgroup\$
    – Paebbels
    Dec 30, 2015 at 0:22
  • \$\begingroup\$ Good too know. I thought they were bad but this book I've been reading seems to put them in every example of a state machine which is why I decided to just use them. \$\endgroup\$
    – chasep255
    Dec 30, 2015 at 0:23
  • \$\begingroup\$ Your synthesis tools has more freedom to optimize your code if you use synchronous resets. It's also nicer for the static timing analysis (STA) to calculate your circuit's paths. \$\endgroup\$
    – Paebbels
    Dec 30, 2015 at 0:25
  • \$\begingroup\$ @chasep255 your book might be referring to IC designs. IC designs typically use a lot of flops with asynchronous resets. FPGAs tend to have few, if any, flops with asynchronous resets. \$\endgroup\$
    – Greg
    Dec 30, 2015 at 4:23

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