I don't use Verilog for anything serious, but I use it in my classes, and I'm starting to think I must be missing something about the appeal of behavioral hardware description.
When I write Verilog I feel like behavioral description is solving the easy problem, namely making a structural description of the hardware; and I'm not really sure if it makes it much easier. But I do find myself spending a lot of time checking and rechecking my
cases to make sure they're really combinatorial when I want them to be.
Maybe I'm just not designing the right kind of hardware to make
always blocks convenient?