# Meaning of strong and weak drive in VHDL?

What is the meaning and effect of "strong" and "weak" drive shown by (0,1) and (L,H) in VHDL's package ieee.std_logic_1164?

The ieee.std_logic_1164 package allows two drive strengths.

(0,1) are normal drive strength and used for all normal purposes. (L,H) are weak drivers, they are normally used to model pull-up and pull-down resistors.

Formally, ieee.std_logic_1164 distinguishes between the std_ulogic and std_logic types, even though they share the same set of values (U,L,H,0,1,X,Z etc).

The difference between them is this : std_ulogic is an unresolved type. It is an error for a std_ulogic signal to be driven by two signal sources (like short circuiting 2 wires together - it's usually a mistake) - such errors will be caught (by the compiler) and fixed (by you!) even before you get to simulation.

On the other hand, std_logic is a resolved type. It is legal to have two or more drivers on a signal. The result is determined by a "resolution function" which looks at all the driving values and combines them into the value you will see on the signal. For example, 0 and '1' combine to produce X (the Unknown state) , and X and anything else produces X so that once Unknowns happen, they propagate through the design to show there's a problem.

But '0' and 'H' combine to produce '0' (because H is weak) and similarly, '1' and 'L' combine to produce '1'. So a strong driver can legally overpower a weak one : no harm done.

Let's look at the 'Z' state : it signifies Undriven, or High Impedance (High-Z). Now Z and H combine to produce H because H, though weak, is still stronger than no driver at all.

This is just a brief summary : for all details see a good VHDL book or even the ieee.std_logic_1164 package source code.

So one use of a weak H is in the so-called "wired-or" configuration, as used in I2C buses.

SDA <= H;   -- permanent pullup resistor
SDA <= 0 when I2C_Master_SDA = '0' else Z;
SDA <= 0 when I2C_Slave1_SDA = '0' else Z;
SDA <= 0 when I2C_Slave2_SDA = '0' else Z;


We are safely combining 4 drivers on the same signal : one I2C master, two slaves, and a permanent weak pullup.

This is one of those cases where IEEE Std 1076-2008 gives a concise answer.

16.8.2.2 The STD_LOGIC_1164 values

The logical values '1', 'H', '0', and 'L' of type STD_ULOGIC are interpreted as representing one of two logic levels, where each logic level represents one of two distinct voltage ranges in the circuit to be synthesized.

The resolution function RESOLVED treats the values '0' and '1' as forcing values that override the weak values 'L' and 'H' when multiple sources drive the same signal.

The values 'U', 'X', 'W', and '–' are metalogical values; they define the behavior of the model itself rather than the behavior of the hardware being synthesized. The value 'U' represents the value of an object before it is explicitly assigned a value during simulation; the values 'X' and 'W' represent forcing and weak values, respectively, for which the model is not able to distinguish between logic levels.

The value '–' is also called the don’t care value. This standard treats it in the same way as the other metalogical values except when it is furnished as an actual parameter to the STD_MATCH functions in the IEEE.NUMERIC_STD package or as an operand to a predefined matching relational operator (see 9.2.3). The STD_MATCH functions and the predefined matching relational operators use '–' to implement a “match all” or “wild card” matching.

The value 'Z' is called the high-impedance value, and represents the condition of a signal source when that source makes no effective contribution to the resolved value of the signal.

From 4.6 Resolution functions:

A resolution function is a function that defines how the values of multiple sources of a given signal are to be resolved into a single value for that signal. ...

You can read how synthesis treats std_ulogic values in 16.8.2.4 Interpretation of logic values.

16.8.2.4.2 Interpretation of the forcing and weak values ('0', '1', 'L', 'H', FALSE, TRUE)

A synthesis tool shall interpret the following values as representing a logic value 0:

• The BIT value '0'
• The BOOLEAN value FALSE
• The STD_ULOGIC values '0' and 'L'

It shall interpret the following values as representing a logic value 1:

• The BIT value '1'
• The BOOLEAN value TRUE
• The STD_ULOGIC value '1' and 'H'

And this should tell us you don't short outputs together. There's also provision for 'Z' inferring tristate buffers.

I don't know what that standard is, to which you refer , but 'strong' and 'weak' refer to how much current a logic gate output can provide to maintain the appropriate voltage level corresponding to what the logic level should be.

E.g. if a logic 1 (H) output is supposed to be 5V, that voltage will drop if you connect a heavy load to it, perhaps to the point where it will no longer be considered a valid logic level.

• Could a 'weak' drive be a pull-up / down resistor and a 'strong' be a transistor drive up / down? Jan 1, 2016 at 10:25
• @transistor yes, that is the usual case, but it could go the other way. One common use of a weak pullup would be to give a defined default logic level (high) when there is no input connected, such as when the real logic source is not present (such as a plug-in card) Jan 1, 2016 at 10:33