# USB signal routing - Swap data lines using vias?

I'm making my second USB design, but the D+/D- pins on the MCU (atemga16u2) aren't in the right order for the micro B connector. What's the best practice for routing these to go the right way? My current idea is to rotate the atmega 180 degrees and route them under, but it feels like the traces are fairly long.

I could also drop one of the lines under the other, but I'm sure that would mess with the lengths for the differential pair.

This device won't go over Full Speed, so I can get away with less than perfect routing.

• If you have enough space, keep the traces on the top layer and enter the connector from the other side. May be worth rotating the chip too. – Armandas Jan 3 '16 at 13:19
• Do you mean the other side as in the bottom layer? Unfortunately I can't do that because of space issues. – monty Jan 3 '16 at 13:22
• No, other side as in from the top (as shown in your image), instead of bottom, as you do now. – Armandas Jan 3 '16 at 13:23
• At USB full speed you can get away with a lot. Vias certainly, 0805 or even 1206 0-ohm resistors to bridge one over the other on a single layer, etc. You already have inline resistors (as many designs do) so you can exploit those. – Chris Stratton Jan 3 '16 at 16:12

Since it's hard to describe it in the comments, I'll put it as an answer.

If space permits, you can route your signals like so:

• You just beat me to it before I uploaded mine: i.imgur.com/nELi3dP.png Now, the datasheet says that should be a signal free zone - should I be fine? – monty Jan 3 '16 at 13:32
• @monty I forgot that the microUSB is all metal. I would advise to follow the data sheet instructions whenever possible. – Armandas Jan 3 '16 at 13:54
• @monty I'll borrow your image for my answer, if that's OK. – Armandas Jan 3 '16 at 16:20
• Is there any benefit to routing both traces around like that? Why not route the one to R2 from the six o'clock position of the upper pad to the twelve o'clock position of the lower pad and then route only the trace to R1 around? – par Jan 3 '16 at 22:33
• @par USB uses differential signalling, so you need to match the trace lengths as well as keep them together to maintain differential impedance. It may not matter too much in this case (due to lower speed, as mentioned by others), but it's a good practice and a habit one should develop. – Armandas Jan 3 '16 at 22:39

If you want to use vias, there is a simple trick to swap the lines: Rotate the vias by 90 degrees, i.e. put them "above" each other. If you enter both vias from the left in the top layer and leave them to the left in the bottom layer, both lines are swapped at no expense:

(Just a quick drawing as my schematics computer just told me it's absolutely necessary to install updates right now...)

At USB Full Speed you don't have to worry about length matching on the differential pair. The electric signal propagates at about 20 cm/ns in the trace.

As the signal is transmitted at 12 MBit/s each bit is 83 ns long. Assuming sampling is done in the middle of each bit period and the rise and fall times of the signals are not longer than 30 ns (which is very conservative), there is still a margin of 41 ns - 30 ns /2 = 26 ns, corresponding to a trace length of 5 meters. Given this, one can safely assume that a mismatch of several centimeters is absolutely no issue at all.

• Another good option. – Armandas Jan 3 '16 at 18:21
• Could you provide a picture? I'm having a hard time envisioning what your describing. – vini_i Jan 3 '16 at 19:38
• @vini_i Here you go - added a drawing of traces. – asdfex Jan 3 '16 at 20:15
• If everything was on the top layer, for example, would you then drop it to the bottom and them bring it back up with the cross over? – vini_i Jan 3 '16 at 21:50
• Can you explain briefly your equation 41ns - 30/2ns? The entire period is 83 ns, and you are removing half the rise time to get the amount of time where the signal is a valid 1 or 0, yes? Why would you also not remove half the fall time? and why are you only using 41ns (half the bit period) instead of the full 83ns? So why wouldn't it be 83ns(full period) -30/2 -30/2=53ns? Are you basically saying you have a margin of +/-26ns in either direction to give you a full 53 ns of margin? – scuba Aug 31 '17 at 12:31