Voltage Mode Control of a DC-DC Buck converter

Question

My previous question was about a hysteretic-style buck converter:

Buck Converter Control Scheme- Why isn't just a comparator not enough?

By what I gather from previous answers, a hysteretic-style buck converter would not work efficiently as the switching frequency is not constant, resulting in output ripple.

Here is the schematic of standard Voltage Control Mode scheme:

The control loop has two main parts: error amplifier and voltage comparator. An error amplifier is a differential amplifier with a high gain.

I understand that to maintain switching frequency constant, the error voltage is compared with a sawtooth(of fixed frequency) and the output of comparator (VR) controls the duty cycle.

What is the function of an error amplifier here?

Even if the output was directly compared with a sawtooth wave, the switching frequency would have remained constant.

What I've read is that an error amplifier is essentially an integrator in this case. How does an integrator help here? Is the function of capacitor is just frequency compensation?

Help me out! This is a difficult topic for me and there aren't many resources available :(

** Update ** The output of integrator would be a ramp with negative slope at very low frequencies. How does that help? Why only an integrator?

Answer 1

Your schematic is showing current-mode control.

In voltage-mode control the error amplifier compares the output voltage to a reference, then provides an output that is compensated and compared to a sawtooth wave that will vary the PWM duty cycle to drive the error lower.

At low frequencies (esp DC) we want the error to be as small as possible, so we want the error amp/compensation to look like an integrator. Any error will then build up and drive the PWM to force the error to zero. Only zero error will allow the output of the compensation to reach steady state at DC.

If we just used an integrator for the compensation we would have to close the loop at a very low frequency which would mean poor transient response (poor rejection to disturbances). That's because an integrator provides 90 degrees of phase shift and we would have to close the loop well below the L-C output filter resonance which provides another 180 degrees of phase shift. We also wouldn't be able to control transients causing the output filter to ring because our control bandwidth would be lower than the LC resonant frequency. Still, we want to put a pole at DC for good DC regulation.

The output filter L-C has 2 poles. So in order to cancel those two poles we can put 2 zeroes in the compensation. Now we still have that 90 degree phase shift until the switching frequency effects and error amp bandwidth start to come in.

With the two zeroes we form in the compensator we get a couple of poles as well (if we want them or not).

So we put one additional pole in the compensation somewhere around half the switching frequency to filter out noise and ripple, and a pole at the capacitor ESR zero frequency to cancel that. Now we can close the loop at a reasonable frequency with a reasonable phase margin and still get good DC accuracy.