I have an MCU controlling a 16bit DAC via SPI (and an additional LDAC output, which triggers the update of the DAC output). The MCU has a precalculated 1120Hz sine wave in a 364-byte long buffer (all calculations in float32, rounded to uint16 for DAC output), sampled at 29120Hz. In a timer interrupt, the update of the DAC is triggered via LDAC and then a new value is loaded from the buffer and sent via SPI. The update to last value is triggered in the beginning to reduce jitter due to memory access races against DMA. Interrupt has a sufficiently high priority to not be delayed.
The highest peak is the required 1120Hz, others are equally spaced by 260Hz. The right peak seems to be only 5dB below the main!!
The jitter on the LDAC pin is on the order of +/- 0.25us, which I'd consider acceptable against 34.3us sample time. The timer itself runs from the MCUs crystal and should be stable enough.
What kind of a problem would lead to such a distortion pattern? What could be the ways to diagnose and reduce it?
Just in case relevant: the DAC is an AD5686, full-scale reference is 5V, sine amplitude is 25mV which results in roughly the lower 10 bits being "switched".