Reading through Altera documentation on FPGA programming, I can see that the design flow is made of
Design -> Compilation -> Simulation -> Programmation -> HW Verification
The design consists of writing Acceleration function units and using IP to build a circuit in schematics, e.g. using Quartus. The design is then compiled. Simulation is made of functional and timing simulation. Functional simulation verifies that the design corresponds to the functionality we want, while timing simulation is to verify the impact of the propagation delay. Only on the programming phase, the file generated at compilation is loaded onto the FPGA and run on hardware for HW verification.
I infer from this that the simulation phase does not need Hardware. Is it correct? Also, the doc mentions the waveform simulation platform for timing simulation. Are there other tools for timing simulation and what are tools for functional simulation?