Reading through Altera documentation on FPGA programming, I can see that the design flow is made of

Design -> Compilation -> Simulation -> Programmation -> HW Verification

The design consists of writing Acceleration function units and using IP to build a circuit in schematics, e.g. using Quartus. The design is then compiled. Simulation is made of functional and timing simulation. Functional simulation verifies that the design corresponds to the functionality we want, while timing simulation is to verify the impact of the propagation delay. Only on the programming phase, the file generated at compilation is loaded onto the FPGA and run on hardware for HW verification.

I infer from this that the simulation phase does not need Hardware. Is it correct? Also, the doc mentions the waveform simulation platform for timing simulation. Are there other tools for timing simulation and what are tools for functional simulation?


2 Answers 2


Simulation tools in this software are a pure digital simulation of the code you have written. No you do not need hardware, and generally it is abstracted completely from the chosen hardware. There are a few intricacies in this such as needing to set defaults on simulated signals and to simulate a clock, This is generally done in something like modelsim, which you could open your code in.


Altera has no own simulator. They ship Quartus with ModelSim Altera Edition. The tool is from Mentor Graphics.

There are other simulators on the market:

  • Mentor Graphics QuestaSim
  • Aldec Active-HDL
  • Aldec Riviera Pro
  • GHDL
  • ...

Xilinx for example develops an own simulator: ISE Simulator; now Vivado Simulator.

Each of these tools can compile source files (VHDL, Verilog, ...) to a simulation model and run it => RTL simulation.

A synthesizer can also emit netlists as source code equipped with primitives. These source files can be compiled for a technology RTL simulation.

Depending on how far you go (map, place, route, ...) the synthesizer can emit even more detailed netlists as source code. It replaces RTL primitives with VITAL primitives for timing simulations.

Because the interface is based on source files, each simulator can run all types of digital simulation if one provides the netlist as primitives.

Note: A more detailed simulation gets slower.

So there is no FPGA device involved. But you need to name one, so the toolchain can choose the correct primitives and timing parameters.

BUT: Hardware tests are still needed!

A simulation model is just a model and an FPGA acts different in some corner cases. Some parts of an FPGA plus the development board can not be modeled, so it must be tested on the physical device.

There are other tools for functional verification, coverage testing, ...


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