For FPGA design, compilation of the design produces a bitstream. What is the input of the simulation (Timing and RTL)? Is it the bitstream itself? Another file? For Altera specifically, what are possible formats for the bitstream and what is the format for the input of the simulation?

Also, what is the synthesis? is it a kind of compilation? what are input and output? is it needed on all FPGA? is it producing input file for simulation or for loading onto FPGA and hardware debugging?


Inputs to simulation are always an HDL file. For behavioural and sometimes RTL simulation, the input is an HDL file you write, that describes the hardware you want, either via its behaviour, or at lower level (RTL).

Nowadays it's normal to write at a higher level than RTL - describing the hardware's behaviour - with care, you can write a behavioural description that is synthesisable, so there is little need to worry about RTL.

Timing simulation is not a routine part of the FPGA flow, unless you are deviating from normal good synchronous practice, or you suspect a synthesis tool bug. With good practice, synchronous design and correct timing constraints, the synthesis and backend tools will generate gate-level hardvware that matches the behavioural description, and static timing analysis will verify its timings much more thoroughly than you ever could via simulation.

However, in case you need it, the synthesis tool and back end (place/route) tools can write out the synthesised and routed designs, as gate level HDL. This is effectively the same as the bitstream, but written out, gate by gate, in VHDL. And it can be many megabytes, leading to very long simulation times.

So the input to timing simulation is also an HDL file, but usually one written by the tools.

Synthesis is a kind of compilation. But instead of producing assembler instructions, it produces a network of gates and flip-flops that implements the original design. This is usually in some kind of object format, though it can be written out as structural HDL, for timing simulation.

That's not the end of the process - the backend tools take the synthesis output and map it to specific gates on the FPGA, and program all the switches controlling the wiring between gates, to interconnect them. This is a challenging task because there may be a million signals between gates, and the tools have to ensure the most time-critical signals have the fastest (shortest) wiring, in order to meet the timing constraints you specify (e.g. you want the design to run at 200 MHz).

Finally the output of these backend tools is the bitstream - which is the only thing you need for the FPGA. Or, for simulation, another HDL netlist, annotated with the actual signal delays.


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