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Suppose we have a type-I PLL whose block diagram is shown below: enter image description here Here \$k_{pd}\$ is the average gain of the phase detector producing the control voltage \$V_c\$ which is input to the Voltage Controlled oscillator (VCO). In the feedback path we have a frequency divider which divides its input frequency by N.
Suppose input frequency is given by \$\omega_{ref} (=2\pi*f_{ref})\$ and output frequency is \$\omega_{out}\$, then in general the phase difference between the input and the fed-back frequency is given by: \$(\omega_{ref} - \omega_{out}/N)t + \Phi_{ref} - \Phi_{out}/N\$.This error signal is input to the phase detector. The steady state phase difference should be given by: \$\Phi_{ref} - \Phi_{out}\$ with \$\omega_{ref} = \omega_{out}/N\$. Does, this frequency relationship hold true even if \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$, which is beyond the range where the PLL will get locked?
In other words, does the frequency relationship between input and output (\$\omega_{ref} = \omega_{out}/N\$) maintained even if the PLL doesn't get locked? If not, what happens to the output signal (in steady state) if PLL is beyond the lock range (given by \$ |\Phi_{ref} - \Phi_{out}| \ge 2\pi\$)?

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If input frequency and feedback frequency (after dividing) are the same then the PLL is potentially going to fall into a state of in-lock because the phase detector doesn't care about phase differences that are multiples of 2\$\pi\$: -

enter image description here

As the "wandering" clock leaves perfect phase alignment with the static clock (left side), the EXOR output starts to produce thin pulses that become wider as the the wandering clock leads the static clock by greater amounts. At perfect anti-phase between the two clocks the EXOR output is a constant "1" and as the leading extends even more, the EXOR output repeats itself as the phase difference between wandering clock and static clock is 2\$\pi\$ (right side).

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  • \$\begingroup\$ Thanks @Andy for response.... You are saying that "if" input and feedback frequency (after dividing) are same. But in steady state shouldn't (ωref−ωout/N)t be zero? Any non-zero value will either increase or decrease the control voltage which the negative feedback loop should adjust to zero finally. Can there be case when this condition is not true in steady state? \$\endgroup\$
    – sarthak
    Jan 5, 2016 at 11:38
  • \$\begingroup\$ I don't follow what you think I'm saying. Any difference in frequency will produce an alternating control voltage whose alternating frequency is nominally the difference frequency. \$\endgroup\$
    – Andy aka
    Jan 5, 2016 at 12:10
  • \$\begingroup\$ Suppose the system starts from rest with the control voltage zero so the VCO is running at its free running frequency. At t=0, an input reference with frequency ωref is applied which would increase the control voltage and hence ωout. After long time when steady state is reached, should ωref = ωout/N hold, irrespective of whether the PLL gets locked or not? \$\endgroup\$
    – sarthak
    Jan 5, 2016 at 12:47
  • \$\begingroup\$ If the two frequencies align there is every likelihood that lock will be achieved shortly afterwards but it's no a guarantee because the analogue filters may cause instability and the VCO(/N) may hunt above and below the desired frequency and never reach permanent lock. Another way to look at this is that if the PLL does acquire "lock" then the two frequencies will be tracking each other but there will be a small phase error that is amplified to drive the VCO. It can be quite complex. Anyway, I believe I've answered your primary question but please let me know if you think I haven't. \$\endgroup\$
    – Andy aka
    Jan 5, 2016 at 12:50

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