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schematic

simulate this circuit – Schematic created using CircuitLab

For simple MOSFET-pair current mirrors, such as the NMOS version above, are there any known disadvantages that one has to consider? The above example, for instance, does not perfectly mirror the current (I really don't know about this, as the LTSpice sim works perfectly).

I'm excluding the discussion about parameter mismatch between the MOSFET pairs (V_TO, λ, K, etc)and the condition I_REF ≤ V1/R_LOAD, but more of noise or bias or anything like that.

What I mean is does this just sorta average out as current mirroring? The same way that a Common Drain sorta averages out as having voltage gain of a little less than unity?

EDIT:

What about frequency response? Can MOSFET-pair Current Mirrors reach GHz range? Or, Is it useless to ask? This being the simplest MOSFET-based Current Mirror?

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  • \$\begingroup\$ It is exactly a current mirror, with the ratio dependent on the ratio of the lengths of the channels. \$\endgroup\$
    – Ignacio Vazquez-Abrams
    Jan 7, 2016 at 9:38
  • \$\begingroup\$ I don't need a Current Amplifier. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 9:53
  • \$\begingroup\$ I suppose one can pretty much guarantee the L and W of a MOSFET when manufactured in the same die, but for different batches or manufacturers, even for same part numbers, it's harder. That's why I excluded those problems, as that is something no one can do about in the design phase. Maybe I'll need special instruments to measure and match everything. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 9:56
  • \$\begingroup\$ "Base"? You mean "gate"? They drain through the channel (some leakages from gate to source. For very, very small signals (small currents), the high impedance across the drain-source channel will allow voltage to build up, and when charged up to V_OV > 0, will allow much larger currents to pass through and deplete the charge at the gates. That will cause the channel to stop conducting, thus creating the impedance that build up at the gate. This happens over and over. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 11:14
  • \$\begingroup\$ I'm comfortable enough with the small signal model above, I've no problems with it. But for larger currents, I really can't derive from the Schichman-Hodges model how the original current coming in would also create (through the low impedance of already active drain-source) enough voltage that is EXACTLY needed to allow the original current. From intuition, I think it the current allowed through M1 should be lesser than fed through it. Maybe I should be looking into the Inversion Depletion Layer Model. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 11:18

3 Answers 3

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One of the reasons could be that since you have an extra load the resistance of the right side is different compared to the left side mirror. So this would cause slight deviation in the mirrored current. Or the mosfet to the right is not in saturation ! Because 100ma is a lot of current and the voltage that it would create at the gate of the left side Mosfet would be high such that Vds of rights side mosfet is small compared to Vgs (Since the same Vgs is given to the right mosfet) therby putting the right mosfet in the triode region. Checck if the mosfets are in saturation first , if they are then the deviation would be purely because of differnces in Vds from the 2 transistors.

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  • \$\begingroup\$ You're probably right. If I'd have to choose, I'd have them both at saturation. I haven't really worked out how to do it. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 9:53
  • \$\begingroup\$ So you could calculate your Vgs. Id= (K*W*(vgs-Vt)^2 ) / 2*L (Saturation region formula for a mosfet). so since you know the Id, K ,W/l (If you haven't, choose a w/l ratio ) and Vt (which should be there in the data sheet for that mosfet) You have only your Vgs tthat is unkown which can be calculated now. \$\endgroup\$
    – Bhuvanesh Narayanan
    Jan 7, 2016 at 10:52
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M1 and M2 have DS voltages that are very different so you cant expect your simulated current gain to be unity .A cascode scheme would work better .In the 1980s I lashed some BJT current mirrors with discrete BD139s to try to make 200mA. The results were terrible .Mosfets have worse spreads than BJTs so if you built this in any quantity it would be a production disaster.Plug some min/max gate source threshold voltages in your simulation and see for yourself .Source resisters will help but thier values will be wastefully high if you want unity gain accuracy.

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  • \$\begingroup\$ Which is why I'll have to find a way to make both exactly the same V_DS and in Saturation Region. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 11:26
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There is ONE bias issue that you can run into with these. You can exceed Vgs limits on M1. Remember that since you've biased the drain and gate at the same voltage that the Vds = Vgs < Vgs_max. Noise isn't really a problem you can avoid, after all, everything adds noise (there's noise from electrons moving).

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    \$\begingroup\$ While this may be a hypothetical problem. with an IRF530 at 100mA, I think Vds=Vgs = something quite small. \$\endgroup\$
    – user16324
    Jan 7, 2016 at 12:24
  • \$\begingroup\$ @BrianDrummond, I was taking it as a more "general" question. To be honest, I didn't think kozner was actually using IRF530's (power mosfets) for a 100mA current mirror. \$\endgroup\$
    – Dave
    Jan 7, 2016 at 12:28
  • \$\begingroup\$ Completely missed this one. I actually thought I could go cheap in the initial stages of the circuit. \$\endgroup\$
    – kozner
    Jan 7, 2016 at 12:35

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