Most (if not all) SD card datasheets contain the following requirements, which I gather are copied from the standard:
- 16nH max trace inductance for f < 20 MHz
- 40pF max line capacitance
Why does the SD standard and/or datasheet need to "micromanage" the amount of trace capacitance and inductance? Can we just meet the timing requirements and be fine? I understand the relationship between too much L-C on the line and signal integrity, and that they go hand-in-hand, but am confused why the standard requires specific L-C values.
Is there an explanation for the "f < 20MHz" condition on the inductance requirement? It seems vague what is required at higher frequencies (our system is clocking the SD card at 50 MHz). Also, why would this be a 'less-than' spec, and not a 'greater-than' spec?
Miscellaneous Background: we built our PCB with an Altera Cyclone V SoC driving a MicroSD card. It wasn't until after the first proto we realized the L-C requirements of the SD card interface. We currently do not meet the L-C requirements given the length of our traces (2.12in for the clock trace). The inductance is 7.8 nH/in, plus three vias at ~1.2 nH a pop brings us to a solid 20 nH, not including the inductance of the SoC's BGA at 8.3nH. We will try to shorten up the traces in Proto 2, but would like to understand the requirements of the SD standard (which we don't have access to directly) before spending considerable effort trying to meet the specs.