2
\$\begingroup\$

Most (if not all) SD card datasheets contain the following requirements, which I gather are copied from the standard:

  • 16nH max trace inductance for f < 20 MHz
  • 40pF max line capacitance

Two questions:

  1. Why does the SD standard and/or datasheet need to "micromanage" the amount of trace capacitance and inductance? Can we just meet the timing requirements and be fine? I understand the relationship between too much L-C on the line and signal integrity, and that they go hand-in-hand, but am confused why the standard requires specific L-C values.

  2. Is there an explanation for the "f < 20MHz" condition on the inductance requirement? It seems vague what is required at higher frequencies (our system is clocking the SD card at 50 MHz). Also, why would this be a 'less-than' spec, and not a 'greater-than' spec?

Miscellaneous Background: we built our PCB with an Altera Cyclone V SoC driving a MicroSD card. It wasn't until after the first proto we realized the L-C requirements of the SD card interface. We currently do not meet the L-C requirements given the length of our traces (2.12in for the clock trace). The inductance is 7.8 nH/in, plus three vias at ~1.2 nH a pop brings us to a solid 20 nH, not including the inductance of the SoC's BGA at 8.3nH. We will try to shorten up the traces in Proto 2, but would like to understand the requirements of the SD standard (which we don't have access to directly) before spending considerable effort trying to meet the specs.

\$\endgroup\$
  • \$\begingroup\$ Adding the the primary answers: you wrote that you don't have SD card specifications. The SD Card association now offers non-proprietary "simplified specifications" at sdcard.org/downloads/pls \$\endgroup\$ – Bryce Feb 21 '16 at 2:26
3
\$\begingroup\$

Trace inductance is series and the capacitance is parallel and, for an un-terminated line will produce a 2nd order low pass filter that will slow down the data edges. I'm going to take a liberty with the math here and assume that the inductance and capacitance are just two lumps - these will produce a cut-off (or natural resonant frequency) of: -

f = \$\dfrac{1}{2\pi\sqrt{LC}}\$ = 199 MHz (using 16nH and 40 pF)

This sounds conveniently higher than 20 MHz by a factor of ten so it's probably one of those "committee" numbers that allows for the possibility of an extra little bit of rise or fall-time edge deterioration due to the PCB traces and ground plane.

A quick simulations shows that the edge rises and falls will be extended by about 3.7 ns from the 90% point to the 10% point: -

enter image description here

I have assumed that the series resistance of the driver is 50 ohm (in series with the inductance of 16nH). It could be that your driver (50 MHz) has better characteristics and can deliver a little bit of controlled overshoot at the load and thus get significantly faster rise/fall times.

Another quick check shows me that if the driver output resistance is 33 ohms the rise and fall times are about 2ns. If the driver output impedance drops to 10 ohms the rise time and fall time drops to about 1ns but there is significant overshoot (about 40%) and this is probably unacceptable.

I believe that the 16 nH and 40 pF limist are committee values to manage rise/fall times and overshoot. They probably work in conjunction with other requirements (maybe driver output impedance?).

| improve this answer | |
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.