# Phase Locked Loop: Confusion in Lock Range

For Phase locked loop (PLL), we can have two types of Phase Detectors (PD): Type-1 and Type-2. The Type-1 PD has an analogue multiplier (which is simply XOR for digital inputs) whose low pass filtered output is a signal which varies at a frequency equal to the difference between the input and Voltage Controlled Oscillator (VCO) frequency. The voltage v/s phase plot of such a PD looks like this:

For this PD, the rising slope provides a negative feedback for the PLL loop but the falling slope provides a positive feedback. Why is that? And, as shown in the figure the PLL locks on the rising slope, so what parameters of PLL decide where on this slope the PLL would lock? Does it depend on the input frequency as well?

The Type-2 PD has a digital circuitry of flip-flops whose output depends only on the relative time shift of the input edges and has the average voltage v/s phase characteristics as shown below:

Why would a PLL with this type of PD not lock if the phase difference input to the PD is greater than $2\pi$?

• Were you satisfied with the answer I provided on your previous question related to PLLs: electronics.stackexchange.com/questions/209580/… Jan 8 '16 at 9:23
• @Andyaka ....Yes I understood what you were saying in the previous question. But I think this is a different question so I asked separately.... Jan 8 '16 at 9:42
• I agree and, the rising slope is the slope that the detector settles on - if it's on the wrong slope it rapidly "moves" to the "correct" slope due to the positive feedback. Jan 8 '16 at 9:58
• @Andyaka Could you please explain what determines where would the PLL lock on the rising slope for the Type-I PLL? By where, I mean what will be the final phase difference when the loop locks and whether it depends on the frequency of the input signal? Jan 8 '16 at 10:23

Have you looked at the datasheet of the 4046 PLL ? The 4046 contains both types of PD.

The type-1 PD implemented as an XOR outputs 0 when both it's input signals are equal and outputs a 1 when they are not. It cannot distinguish between both signals so it cannot detect if Fvco is too high or too low. It can only detect that it is "not the same" as Fin.

At phase = π the signal inverts so at phase = π - delta the PD's output signal is the same as what it is at phase = π + delta. This explains the positive slope changing to a negative slope at phase = π. The input signal inverts but the XOR treats it the same way, it cannot do any better !

"Why would a PLL with this type of PD not lock if the phase difference input to the PD is greater than 2π?" Your assumption is wrong, it does lock. Let me explain:

I give you two signals and a 4 channel oscilloscope. At t = 0 I provide you with 3 signals:

signal A is a 1 kHz sinewave starting at phase = 0

signal B is a 1 kHz sinewave starting at phase = π

signal C is a 1 kHz sinewave starting at phase = 10 π

Now tell me which signal is which ! Think about it before reading any further !

The answer is that you can only tell me which is signal B. You cannot distinguish signals A and C because a sinewave repeats itself every 2π of the phase.

Like you, a type-2 PD also cannot distinguish signals which are shifted by 2π so it will treat a phase of delta the same as a phase of delta + 2π or delta + 4π. That is why the graph only shows 0 to 2π, the graph repeats itself every 2π just like a sinewave.

It can however distinguish a phase of π - delta from a phase of π + delta ! That is it's advantage over a type-1 PD.

For a type-2 PD it is not the absolute phase that is locked, it is the modulo(2π) of that phase and that is OK as the signal repeats.

• For the Type-I PLL I am not asking why the slope is changing....But I am asking why the type of "feedback" of the PLL loop changes to positive feedback when phase is beyond π. And for the Type II PLL how did you conclude that it does lock for phase greater than 2π. Again, I am not asking why does the plot looks like what it looks Jan 8 '16 at 9:38
• One leads to the other, the transfer function of the PD changes from positive to negative around π. The PD is inside the feedback loop so the feedback then also changes sign. You still do not seem to get that a signal with a phase of delta is identical to a signal with a phase of delta + 2π. So there is no difference compared to the situation where the phase difference is between -2π and +2π, therefore the plot for a type-2 PD always applies so it will lock. You can always substract 2π phase from Fin and/or Fvco and end in the situation where the type-2 PD plot applies. Jan 8 '16 at 9:56
• Thanks for the helpful comment....so does that mean that for the Type-II PD, the PLL will always lock no matter what is the phase difference? Jan 8 '16 at 10:26
• Yes it will always lock, provided all other required conditions are met. For example: Fvco must be capable to reach the same value as Fin. If the PLL cannot lock usually Fvco will be at an extreme value (maximum or minimum frequency). Jan 8 '16 at 11:24
• And if you REALLY want to understand PLLs, you will need to build one. Start with that 4046 I suggested on a breadboard. This is very educational !I also started with the 4046 (25 years ago ;-) ) now I design on-chip PLLs myself :-) Jan 8 '16 at 11:30

Could you please explain what determines where would the PLL lock on the rising slope for the Type-I PLL? By where, I mean what will be the final phase difference when the loop locks and whether it depends on the frequency of the input signal?

The VCO produces a frequency that can be shifted by a control voltage. That control voltage is totally derived (via filters and amplification) from the "error" signal from the phase detector. That's the back story and you should be OK with that so far.

In a perfect mid-range-frequency scenario let's say the control voltage is 2.5 volts. If that voltage were increased, the VCO output frequency would lower and, if that voltage were lowered, then the VCO output frequency would increase.

This ensures that negative feedback is on the rising slope of the EXOR but, equally, if the VCO control were inverted then negative feedback would occur on the falling slope.

Let's also say that the EXOR phase detector ran on 5V logic supplies. This now means that the mid-range average output voltage is also 2.5 volts. This happens when the phase of the two signals at the EXOR input are 90 degrees apart - that is what we would call true lock for a type I detector.

This scenario (absolute bang-on mid-range) produces no phase error and we would see two identical frequencies that are frequency locked and phase-locked at 90 degrees.

Now consider the scenario where we are asking the VCO to be not at mid-range. Lets say that the control voltage needed to obtain lock would be 3.75 volts. Let us also say that for the EXOR to produce an average voltage of 3.75 volts, the phase difference between its two inputs has to shift in order to accomplish this and this is the bottom-line that I think you are asking about.

3.75 volts coming from the EXOR means the phase cannot be 90 degrees if there is to be enough voltage to drive the VCO into lock. This scenario is not an altogether practical solution because there is usually a gain block inserted between the filtered output of the EXOR and the input to the VCO.

The gain block has the effect of requiring a smaller phase error to drive the VCO to the correct frequency. On the down-side, the gain block can cause instability and more phase jitter when the PLL does acquire lock.

Is this what you are looking to understand?

• Thanks....But I think the conditions for the VCO voltage to ensure the negative feedback should be converse of what you said. Do you agree? Jan 8 '16 at 14:33
• Darn I changed it once a couple of hours ago - maybe I was better leaving it. Yes, it could be that the VCO goes the other way when the control voltage rises. Thinking..... Jan 8 '16 at 14:35