I'm familiar with the utilization of Schmitt Triggers when interfacing with low slew rate signals / sinusoidal waveforms. In a recent design, I've been scrubbing our FPGA I/O configurations and noticed that I left the Schmitt Trigger on for a lot of I/O pins that don't necessarily need it (those pins are fed by MCUs / buffers that have slew rates on the order of nanoseconds, so very fast).
I can come up with a reason to use Schmitt Triggers for a slow rising signal, but I cannot answer the question for myself, are their downsides to using a Schmitt Trigger on a fast input? These signals are slow in the sense that they aren't periodic (power enables, etc.) but do have fast edge rates (say 5-10ns rise/fall times).
I've turned them off in my design -- this question is more for my own edification than anything else, and to be able to justify why they should be off.
FPGA in question is the Actel IGLOO (don't think it has any bearing, but just FYI).