Update: the follow-up question shows my take on the resulting PCB layout.
I'm laying out my first board with a uC (I've got a reasonable amount of experience in using and programming embedded systems, but this is the first time I'm doing the PCB layout), an STM32F103, this will be a mixed-signal board using both the internal DACs of the STM and some external DACs via SPI, and I'm a bit confused about the grounding.
The answers to these questions:
- Decoupling caps, PCB layout
- Competing PCB Crystal layout recommendations
- Mixed signal PCB layout for PSoC
clearly state that I should have a local ground plane for the uC, connected to the global ground at exactly one point, and a local power net, connected to the global power near that same point. So this is what I'm doing. My 4 layer stack is then:
- local GND plane + signals, uC, it's 100nF decoupling caps, and the crystal
- global GND, unbroken except for vias. In accordance to sources such as Henry Ott, the ground plane is unsplit, with the digital and analog sections physically separated.
- power, a 3.3V plane under the IC, thick traces for the 3.3V external DACs, thicker traces for distributing the \$\pm15\$ volts in the analog section.
- signal + 1uF decoupling caps
Further away on the board the analog components and signals are on the top and bottom layers.
So the questions:
- should I break the global ground under the uC, or is it good to have the full ground plane under the local one?
- Power plane: I'm intending to have a power plane only under the uC and use vias to bring the power to the decoupling caps and therefore the uC on the top layer, as I can't really use one much elsewhere. The external DAC's should be star distributed, so I have separate tracks for them, and the rest of the board is \$\pm15\$ volts. Does this sound ok?
- I'm using both the ADC and DAC of the uC, and generating a reference voltage in the analog section of the board, which I bring to the Vref+ pin of the uC with a track on the power plane. Where should I connect the Vref- pin: local ground, global ground, or make a separate track on the power plane connecting it to the global ground in the analog section, where the ground should be quiet? Maybe near to where the reference voltage is generated? Note that on the STM32 the Vref- is distinct from the analog ground VSSA pin (which I suppose goes to the local GND plane?).
Any other comments on the design here are of course welcome too!