How do I calculate phase margin for a feedback amplifier

Question

I'm learning analog design and can't seem to get a firm grasp on the concept of phase margin and wanted to ask a few questons:

• First Part: I understand that Phase margin is the difference between the phase at unity gain and 180

Question 1: If I have an inverting amplifier, my output phase starts at 180. When the phase remains 180 up to the 3dB frequency, is my phase margin now the distance from 0deg?

Question 2: Is there an equation to calculate the phase margin? What happens when I have negative phase shift, am I now comparing to -180deg?

• Second Part: I followed this video from Linear.com, and I used the following circuit with the LT1212 op-amp to run an open loop analysis:

^{simulate this circuit – Schematic created using CircuitLab}

Running this in LTSpice shows two different 0dB crossing in the bode plot (1MHz [55deg] and downward slope, 7MHz [-86deg] and upward slope). Am I right to assume this circuit would be unstable?

Answer 1

Normally you plot abs(Gain) at y-Axis, so you can calculate the phase margin like an noninverted opamp. This means you start at 0 degree. Or you can handle your problem as in your attempt, but this isn't industry standard.

Answer 2

While speaking about gain and phase, it is important that you know about WHICH amplifier properties you are speaking: And if you are interested in the stability margins you have to investigate the LOOP GAIN only (in contrast to the closed-loop gain). Your drawing is correct because you have opened the loop at the inverting input terminal (this introduces no significant errors because the opamps input resistance is very large.) Then. the loop gain is the ratio of the voltages between both resistors (output of the loop) and the voltage at the inv. terminal (loop input).

If you plot the gain vs. frequency and the phase vs. frequency it is very easy to apply the stability criterion.

EDIT: Be sure to perform an ac analysis over a suitable large frequency range (not a TRAN analysis as indicated in the drawing).