How can I construct an 8 x 1 multiplexer from two 4 x 1 multiplexers with enable inputs?

Question

I've thought about this problem for two days, and I can't figure out the trick. It would be easy with an inverter and an OR gate, but I was told not to use anything but muxes and wires. I figured out how to build a 6 x 1 multiplexer from two 4 x 1 muxes, but that's not sufficient. Can you give me a hint?

Answer 1

I think the trick is that with 2 4x1 MUXes you actually get 4 Input Select signals and 2 Enable Inputs to play with, for a total of 6 control bits. You only need 3 control bits for a real 8x1 MUX (4 if you need an enable). IF you get a bit liberal/imaginative with your control interface to 8x1 MUX you can define a control protocol that works.

Let S0, S1, E0 be the select input bits and enable bit for the first 4x1 MUX. Let S2, S3, E1 be the select input bits and enable bit for the second 4x1 MUX.

The outputs of the two 4x1 MUXes should be wired together.

Whatever logic controls the 8x1 MUX needs to ensure that E0 = !E1 at all times to avoid a short circuit condition. For Input Select = 0 - 3, it should set E0 = 1 and E1 = 0. or Input Select = 4 - 7, it should set E0 = 0 and E1 = 1.

As you more or less correctly stated, control logic for the circuit could be implemented as follows:

Let S0', S1', and S2' be the logical select inputs for the 8x1 MUX:

  INPUTS             OUTPUTS
S2' S1' S0'   S1  S0  S3  S2  E0  E1
 0   0   0     0   0   0   0   1   0
 0   0   1     0   1   0   1   1   0
 0   1   0     1   0   1   0   1   0
 0   1   1     1   1   1   1   1   0
 1   0   0     0   0   0   0   0   1
 1   0   1     0   1   0   1   0   1
 1   1   0     1   0   1   0   0   1
 1   1   1     1   1   1   1   0   1

Plainly from this truth table:

  S0 =  S2 = S0'
  S1 =  S3 = S1'
  E0 = !S2'
  E1 =  S2'

So you will need an Inverter gate at a minimum for the control logic. As far as I can tell you can't do it with "just wire."

Answer 2

The problem doesn't state whether the enable inputs are active low or active high, let alone that the two muxes must be identical in this regard.

Moreover, it is reasonable to assume assume that when the enable input is deasserted, the mux output goes into a high impedance ("high Z") state.

Therefore, the solution is:

• choose two 4x1 multiplexers which have enable inputs that have opposite logic: one has an active-high enable, and the other an active-low enable.
• fan out the high address bit to both enables.
• tie the outputs together: since at any time, one of the two mux outputs is high Z, this is valid.

The opposite enables give us an inverter for free, and the high Z output behavior spares us the OR gate.