I was reading about block ram and I came across the following post. I notice here that whoever wrote the code is using negedge on the clock signal. Thus far almost all the examples I have seen of verilog use posedge on clock signals. In fact I have not really seen any always blocks with negedge specified. I am just wondering when you would want to use that and why might the code bellow contain negedge?
module RAM_param(clk, addr, read_write, clear, data_in, data_out); parameter n = 4; parameter w = 8; input clk, read_write, clear; input [n-1:0] addr; input [w-1:0] data_in; output reg [w-1:0] data_out; reg [w-1:0] reg_array [2**n-1:0]; integer i; initial begin for( i = 0; i < 2**n; i = i + 1 ) begin reg_array[i] <= 0; end end always @(negedge(clk)) begin if( read_write == 1 ) reg_array[addr] <= data_in; if( clear == 1 ) begin for( i = 0; i < 2**n; i = i + 1 ) begin reg_array[i] <= 0; end end data_out = reg_array[addr]; end endmodule