I am completely new to PICs and I have never worked with a part as complex as this. In particular, I'm wondering if it is possible to generate a reference clock (REFCLKO in the datasheet) at 11.2896 MHz while running on the internal 8MHz oscillator (the 8MHz is boosted by a PLL up to 40 MHz which is the core clock). I tried doing this and I looked on the scope only to find that this synthesized waveform had very apparent jitter (measured 25 ns = 1/40MHz jitter) and the frequency didn't look correct. Slowing REFCLKO down to speeds lower than 8MHz resulted in a nice waveform.
It seems logical to me that you could use the provided registers to derive a 11.2896 MHz clock on REFCLKO from the 40 MHz core frequency. Why does this not work correctly? Will I need an external crystal oscillator with frequency greater than 11.2896 MHz to make this work?
I saw a blog post on eev blog that said something to the effect of: even though the core frequency is boosted up to 40 MHz from 8 MHz, the maximum possible external frequency is 8 MHz, but there was no explanation as to why. Please help!!!
It appears that the frequency of REFCLK is not limited to 8 MHz, but rather the frequency is unstable if the ROTRIM register is nonzero. the ROTRIM sets the fractional part of the divider. This way I can get a stable 10 MHz (40 MHz divided by 4.0) clock for example, but fine tuning with a fractional divider results in a bad waveform.