Many IP cores especially from Xilinx have an AXI interface from ARM. (AXI, AXI-Lite, AXI-Stream, APB, ... are parts of AMBA - ARM's bus architecture).
The AXI interface standard is free for download (after registration), but I don't think it's free for implementation. So I asume Xilinx has bought an AMBA license to eqip its IP cores with AXI interfaces.
I don't have such license.
Can I offer AXI interfaces for my (open source) IP cores written in VHDL or Verilog?
It's a bit off topic, but how expensive could it be? How could I get one? :)
I don't know of any Xilinx document, stating if it's legal to build AXI components interfacing with Xilinx AXI cores. Xilinx cores are bound to Xilinx FPGAs and tools by the Xilinx license. This does not effect own components.
On the other hand these components need to implement an AXI interface to interact with Xilinx cores. How can I atleast design such components without an AMBA license?