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I was going to start learning how to use a 555 timer as an oscillator, however am greatly confused in the pin configurations example schematics provide me.

To show visually what I mean, A random wikipedia schematic on the main 555 page shows this:
555 circuit

My Eagle CAD software shows this:
Eagle 555 pin diagram

However the "actual?" chip package pin diagram is much less confusing:
555 pin diagram

Can I assume that most of the 555 chips from different manufacturers are interchangable (same pin configuration), however the programs/diagrams have pins that way just to look simpler?

I can always route my own weird ways on the actual chip to match the configuration in the schematics, however that is confusing due to it changing each time.

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    \$\begingroup\$ Well, you should see the 666 pin diagrams. They are positively evil! \$\endgroup\$ – user3624 Oct 20 '11 at 3:26
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    \$\begingroup\$ Note that the pin numbers and names agree on all three diagrams, just their placement in the schematics symbols is different. \$\endgroup\$ – starblue Oct 20 '11 at 7:15
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    \$\begingroup\$ I understand your question... One day I will go crazy and kill one of those schematics symbol designers! \$\endgroup\$ – hkBattousai Oct 20 '11 at 18:00
  • \$\begingroup\$ It's pretty dumb when the physical layout is less confusing than the virtual. I mean, the symbol designer has all the freedom to arrange things logically, not constrained by concerns like how the wires go from the IC pins to the die. \$\endgroup\$ – Kaz May 18 '13 at 5:26
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The physical pin-outs of all "555" devices that I know of are the same.

In general, schematic symbols are generated to match the standards and/or prefernces of the organization or engineer that is using the component. Sometimes, a PCB designer creates the schematiic symbol in any way that seems fit. Many times a designer will use whatever schematic symbol they can find in a manufacturer or third party library.

Some like to make the symbols match the manufacturer data sheet. Others like to make the symbols match the physical pinout (so they can visualize a layout while looking at the schematic or, when debugging, figure out what pin to probe more quickly). Some will arrange symbols to have inputs on the left and outputs on the right. Some organizations allow pins on the top and bottom of symbols, some don't, and some only allow power and ground pins. Some symbols (for digital devices and op-amps etc.) are drawn without power or ground pins; these pins are "globally" connected to the power rails.

In my opinion, many of these standards do not make sense for many chips. In my mind, a schematic should show the "scheme" of the circuit; accurately capturing design intent and allowing easy design analysis.

The bottom line is that you may see as many schematic symbols for a part as there are engineers to create the 'perfect" symbol.

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  • \$\begingroup\$ This gives me a lot of confidence, I am glad I can decipher these layouts, it even gives me the chance to practise PCB design to rearrange each actual pin. Thank you. \$\endgroup\$ – Hobbyist Oct 20 '11 at 2:56
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    \$\begingroup\$ IMHO, anything that makes the schematic harder to read and understand is a bad thing. I once saw a student that drew a symbol for a 100-pin QFP CPU to have the pins in exactly the same places as the package. The schematic was almost impossible to read; the power and ground symbols were scattered all over the place, and the buses were all run together like spaghetti. It was too late to change it, though (he was only here for another month), so the student's project was abandoned. \$\endgroup\$ – Mike DeSimone Oct 20 '11 at 13:28
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    \$\begingroup\$ @Mike, that is a shame he had abandoned it. I'll try to match physical layout as much as I can - readability to me - not the software is more important, It is why I left software programming. :) \$\endgroup\$ – Hobbyist Oct 24 '11 at 9:55
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    \$\begingroup\$ That path leads to madness once you have more than two routing layers or put parts on both sides of the board. It hides the relative component sizes, which are critical to layout. It is also much harder to organize into a multi-page schematic. Seriously, trying to match the physical layout might be just fine for a 555 circuit, but it is just like spaghetti code: fine for student assignments, but impractical on larger things. \$\endgroup\$ – Mike DeSimone Oct 24 '11 at 18:04
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The 1st diagram makes logical sense in the context used and makes diagram easy to understand and makes the function of each pin clear.

The 3rd diagram reflects physical reality.

The 2nd diagram is (probably) the result of somebody being lazy and making a layout suit to suit their wiring and then standardising that layout for no (obviously) good reason. It just may reflect the internal IC layou but that's much more likely to be what is seen in the 1st diagram.

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    \$\begingroup\$ Exactly. A logical diagram ought to be logical, whereas physical layouts have to reflect physical realities. \$\endgroup\$ – Optimal Cynic Oct 20 '11 at 7:07
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    \$\begingroup\$ It can be worth thinking about what the primary purpose of the schematic is. If understanding the function is complicated, then draw it to present that clearly. On the other hand, if the function is simple, but the implementation may be challenging, then it can make sense to draw it to more closely resemble what the person probing around trying to figure out why this particular assembled example doesn't work is going to be looking at. \$\endgroup\$ – Chris Stratton Oct 20 '11 at 13:10
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    \$\begingroup\$ The second diagram is that way because the Eagle library writer had to pick something. (Full disclosure: I am not a fan of Eagle; [big rant about lack of great EE tools omitted].) Anyway, in an ideal world, you'd be able to adjust the symbol and shift its pins around right on the schematic so things looked better without having to open up a symbol editor window and possibly overwrite the existing symbol. (You know, like you could routinely do with paper and a drafting table in the old days and still can do today with paper.) \$\endgroup\$ – Mike DeSimone Oct 20 '11 at 15:51

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