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I am trying to come up with a circuit that generates a series of clocks, I will need these different clocks on different pins. The circuit must be configurable in terms of frequency and phase shift (see below)

All clocks are synchronized. The first clock will be on for 1usec and off for 9usec. The second one will have the same frequency but it will be out of phase by x degrees. The number 3,4,5,6,7,8,9 are exactly the same but they will all be out of phase with their respective shifts.

I can use my CPU but I will have to change frequencies and phase shifts down the line and I want complete flexibility. Assuming I don't use an FPGA, is there a way to generate these clocks with such flexibility. (The flexibility is design time, not user selectable)

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You can get the exact result that you want
by using a CD4017, 1 of 10 counter-decoder,
or the much faster but functionally identical 74HC4017 or 74HCT4017.
(83 MHz 74HC4017 in stock at Digikey for 62 cents in 1's. )

CD4017 datasheet

74HC4017 / 74HCT4017 datasheet

enter image description here

The 4017 is designed to cycle through 10 states maximum, with 1 on (high) at a time, but can be made to produce any lower number by resetting to state 0 when the counter runs past the desired point.

If you are prepared to tolerate a small reduction in pulse width on output zero (leading edge rise time is delayed) you can implement the complete circuit with a 9 x clock input, a 4017 and one inverter. If you want equal pulses on all output a few extra gates will produce the desired result.

The block diagram shows what is involved in "rolling your own" should you so desire.

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It sounds like a circular shift register will do this. Have the processor produce the shift clock probably via PWM hardware or something else that runs without firmware intervention once set up. The output frequency will be the shift clock divided by the number of bits. If the shift register is originally loaded with a adjacent chunk of half the bits on and the other half off, each output will be a square wave with 1/bits fraction of a cycle out of phase with the next.

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You can get a great deal of flexibility using a PSoC3. You can generate all kinds of clocks and cool stuff. You can even write your own Verilog to create your own peripheral. Of course, this is no use if you can't change your CPU.

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