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The RAM and ROM megawizards in Altera Quartus II give the following option in the GUI "Which ports should be registered?" The options vary but are:

‘data’, ‘wraddress’, and ‘wren’ write input ports
‘raddress’ and ‘rden’ read input port
Read output port(s) ‘q’

How do I know if my design requires the outputs of the memory block to be registered or not? If it is a good practice I guess it would be registered by default right?

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Putting pipeline registers at the inputs and outputs of a block RAM allow it to run at the fastest possible clock speed (throughput), but the rest of your design must account for the additional clock cycles of latency before you see the results.

Therefore, you must select the options in the megawizard that correspond to what your logic design actually requires. You can't change them without changing other parts of the design as well.

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    \$\begingroup\$ Thanks David, your answer is great as always. But isn't memory block itself made up of registers anyway? \$\endgroup\$ – quantum231 Jan 12 '16 at 21:20
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    \$\begingroup\$ Yes, but registers with so much other logic around them (address decoders, multiplexers) that signals can waste most of a cycle getting into or out of the memory. So if you're designing for high speed you need a register on the output. \$\endgroup\$ – Brian Drummond Jan 12 '16 at 21:49
  • \$\begingroup\$ OK, therefore putting registers at the input and output allows the tool to workout register to register delay which is used in the calculation of the maximum clock frequency that the design can run at. I now understand what you mean. I did not take into consideration the other logic that you have pointed out. \$\endgroup\$ – quantum231 Jan 12 '16 at 22:31
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The memory can operate in two modes:

  • flow-through mode - registered inputs, unregistered outputs
  • pipe-line mode - registered inputs, registered outputs

In the pipeline mode the overall throughput of the device is improved. Also it makes the output be synchronized on the clock, which is not the case with flow-through memory.

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    \$\begingroup\$ Thank you for your answer. I have just run a simulation of the ROM block in ModelSim and observed that as you mentioned and as I expected, the output is delayed by 1 clock cycle when output is registered using the GUI. The reason I have put this question here is that a memory block is already a synchronous block. It makes sense to register output of a combinatorial block. However, a memory block is already based on register is it not? \$\endgroup\$ – quantum231 Jan 12 '16 at 21:18
  • \$\begingroup\$ ROMs are basically combinatorial. RAMs are not. But the output logic can be combinatorical. \$\endgroup\$ – Eugene Sh. Jan 12 '16 at 21:19

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