0
\$\begingroup\$

i want to do GPS 1 pps aligment clock signal generator. Clock signal should be at 24.576 Mhz and voltage level Vmax= 3.3 V and Vmin=0 V DC. How can i do that? It is very important to align between GPS PPS and Clock signal. While looking these components on the internet, i have found MAX24188 and DS31400. I am not familiar with these components. Is it possible to make this with Max24188 and DS31400? If yes can anyone explain me basicly how?

\$\endgroup\$
  • 1
    \$\begingroup\$ Can you explain what you mean by align, and why they need to align? Are you just trying to maximize frequency accuracy of the 24.576 MHz signal? \$\endgroup\$ – mkeith Jan 13 '16 at 9:25
  • \$\begingroup\$ I mean 1 PPS signal and my 24.576 Mhz clock signal should start its rising level at the same time. (When pps comes, clock signal should be generate from signal generator) You can say GPS diciplined Clock signal. I will use this clock signal for sychronization of my Devices. \$\endgroup\$ – Cem Jan 13 '16 at 10:05
  • \$\begingroup\$ Perhaps buying a GPS disciplined OCXO (10MHz) and then using a PLL to set yours arbitrary frequency. \$\endgroup\$ – Marko Buršič Jan 13 '16 at 11:00
  • \$\begingroup\$ Disciplining a 24.576 MHz oscillator with a 1Hz pulse is quite a challenge, requiring a highly stable oscillator in the first place. Also, any noise or jitter in the 1Hz pulse is going to increase the difficulty. Good luck! \$\endgroup\$ – Brian Drummond Jan 13 '16 at 11:31
  • \$\begingroup\$ Does your GPS not produce a 10 MHz reference tone, or only a 1PPS? It's much easier to go from 10 MHz to 24 and 1PPS, than the other way... \$\endgroup\$ – tomnexus Jan 13 '16 at 14:42
2
\$\begingroup\$

I have done this sort of thing several times in the past for several embedded systems, and it really isn't all that difficult. I typically use a COTS VCXO and an FPGA to implement the logic — nothing exotic.

First of all, what you really want to do is generate a "replica" 1 pps pulse using your 24.576 MHz clock. Then, you use feedback that varies the VCXO control voltage to phase-align this pulse with the reference pulse coming from the GPS receiver, which also means that your VCXO is then frequency-locked to the GPS timebase.

Use the replica pulse to drive the rest of your logic, rather than the reference pulse. The former, by definition, will be precisely phase-aligned with your local clock.

Just how precisely you need the rising edges of the two pulses to be aligned will ultimately determine how difficult this will be. Most GPS receivers provide a pulse that has on the order of ±50 ns error (jitter). Getting your replica pulse down to a similar level is really not all that difficult.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ That implementation makes perfect sense Dave -- does anyone make an ASIC that does the similar so you don't have to deploy a full FPGA to a system? Any clock generators? \$\endgroup\$ – Krunal Desai Jan 13 '16 at 17:16
  • \$\begingroup\$ Not that I know of, but then I never needed to look for one. These were all projects that were using FPGAs anyway, so the additional logic required for the timebase came for free. If you just need a standalone timebase, a medium-sized CPLD could probably handle the logic. \$\endgroup\$ – Dave Tweed Jan 14 '16 at 0:18
0
\$\begingroup\$

You basically need to build a PLL to make that work. How you exactly you should do that depends the requirements of the output signal. It's never going to be exact, so you need to specify a tolerance for the allowable frequency and phase error.

| improve this answer | |
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.