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Today I came across the 74HC164 8-bit serial-in/parallel-out shift register. Reading its datasheet, I realized that it has two serial inputs, instead of one like other shift registers, such as the 74HC595, that I'm familiar with.

On top of that, the two inputs go through an AND gate, as in the picture below (figure 1 on the datasheet):

74HC164

The datasheet says:

Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input.

That tells me that I can use one input to control whether the IC is taking data serially in or not. But a few questions remained:

  • Why do the inputs go through the AND gate?
  • Why not set one fixed pin as input and the other as input enable?

I understand that this feature gives the engineer some flexibility to use either pin as the input and the other as enable, but I fail to see how that's useful in a concrete design scenario, as opposed as having a fixed pin for the input and another for the input enable.

So, if this is not too broad a question to ask, what would be a concrete electronics design scenario in which an engineer would want to have this kind of two input shift register?

I did google for an answer, but didn't get any meaningful results.

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    \$\begingroup\$ I think I have seen it being implemented as and gates in a lot of places, just it was rarely mentioned to be the case. One might want to check if for serial input and input enable pins on others it won't just work that way; after all it seems to be like one of the cheapest ways to implement input enable. \$\endgroup\$ – PlasmaHH Jan 13 '16 at 12:07
  • \$\begingroup\$ How would it be different if you call one pin input and the other input enable? It's symmetric. \$\endgroup\$ – Spehro Pefhany Jan 13 '16 at 13:23
  • \$\begingroup\$ @spehro - My question was more whether it's useful for the user if the pins are interchangeable. \$\endgroup\$ – Ricardo Jan 13 '16 at 14:16
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    \$\begingroup\$ Right, but they're naturally interchangeable so hiding that information seems like it's not of any value. A less symmetric situation - consider the 74HC4017 which has a clock and an /enable input, but they can be used as a /clock and enable inputs. \$\endgroup\$ – Spehro Pefhany Jan 13 '16 at 14:40
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    \$\begingroup\$ @Ricardo I suspect it's lost in the sands of time. Maybe something like a UART implemented with discrete logic. Plus they had an extra pin on the 14-pin package (only 13 were otherwise used) and it made sense to use it for something. You see that a lot. \$\endgroup\$ – Spehro Pefhany Jan 13 '16 at 16:37
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The 1st scenario that comes to mind is capture/compare for 2 signals over 8 stages. Such device can be used in a quadrature decoder, allowing the MCU to have 1/8 interrupt rate compared to a single AND gate.

At each clock pulse, a new comparison is made, after 8 pulses, you have your result. With some extra logic, you can implement states where at least m comparisons out of n are 0 (n<=8) and so on.

There is already an input enable signal, the CP pin.

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  • \$\begingroup\$ That's the kind of answer I was looking for, thanks (+1)! But it's a bit too thin for me to fully understand it. Would you mind elaborating a bit on it, maybe with a schematic or a reference/link? \$\endgroup\$ – Ricardo Jan 13 '16 at 14:12
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The one end of AND input just acts like a input enable for the input.As you know,in AND gate,when two inputs are HIGH,then the output will be HIGH.You can consider the input pin like this modified

    In some shift registers like 74HC595 there is a output enable pin.These are designed for purpose.
    In some case,you want to block the undesired input,In some cases,you may need to block the output,until you get the desired value or until the completion of the clock
    Now take of 74HC595,It can be used as Binary counter.Under such situation,you want to shift 0000 0011 to the shift register.At the same time,you should not notice the shift of the one's and zero's.In such situation output enable.The after completion of 8 clock cycles,the output enable is enabled.
    Likewise in this 74HC164,you can connect multiple of chips in parallel with Input DSA.Now for controlling a specific register,the input DSB is given HIGH,so that it'll be in working state.
    Consider the following diagram.
    situation
    Sorry for the wired diagram.In the case,like in the diagram,you can use only only one shift input from the micro-controller( some micro-controllers will have limited PWM's) and 3 control inputs.This will be more or less resembles like SPI interface with more inputs connected and individual enable pins.
    In this case,some controllers with less PWM or even 1 PWM can be easily controlled.This always allows flexibility to us.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ In your last diagram, assuming I am trying to write data to shift register1 only. Control2 should be in off state (grounded). If both registers are connected to same clock then 0's would be sent to register2 as I write to register1 effectively turning all it's pins off. Am I missing something? \$\endgroup\$ – Ramast Feb 21 '18 at 14:55
  • \$\begingroup\$ I think if you want to be able to control both shift registers then you would want to connect both DSA pins together to a single MCU pin and connect each clock to an independent pin. That way you could write your serial data to both controllers but only the controller that gets clock signal would react \$\endgroup\$ – Ramast Feb 21 '18 at 15:01
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Without the ANDed data inputs, the chip would use only 13 of its 14 pins, and one of the pins would have to be designated a NO CONNECT, which is wasteful and was a NO-NO for TTL MSI 40 yearts ago.

The logic/chip design team then had to figure out a way to use the 14th pin in the most cost effective way to get as much bang per buck out of the chip, and my guess is that they decided that ANDing two DATA inputs was the best way to do it.

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The initial intent was probably to have input and enable pins, which is easily implemented with an AND gate. The spec could just have listed one pin as input and the other one as enable, but since AND operation is commutative, it was decided to expose that implementation detail in the spec and label the pins dsa and dsb to reflect that.

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