Sample And Hold Adder

Question

I've been playing around with a sample and hold adder circuit. Essentially, I am trying to sample a sine wave with a sample and hold circuit. I want to take that sample and add it back to the sine wave to set its DC value. This is what I've come up with but its not happening the wave I imagined it. What is going wrong here?

^{simulate this circuit – Schematic created using CircuitLab}

• Red = Sine Wave
• Blue = Sample
• Green = Summing Amp

I know I am forgetting a fundamental concept here. Can someone explain to me what's going wrong here?

Answer 1

Lets take a look at your schematic.

The voltage at the output of the summing amp is \$Vsum = frac{V1 + Vsample}{2}\$.

When your switch is engaged (closed), the output voltage is \$Vsample = Vsum\$.

If we substitute our first expression into this equation, we get:

\$Vsample = \frac{V1 + Vsample}{2}\$

\$Vsample = \frac{V1}{2} + \frac{Vsample}{2}\$

\$\frac{Vsample}{2} = \frac{V1}{2}\$

\$Vsample = V1\$

So when the switch is engaged, the circuit will tend to push \$Vsample\$ towards the value of \$V1\$. When the switch is off, the sample stays the same (assuming no current loss through the op amp), and the value of \$Vsum\$ should be irrelevant.

Now that you have a proper sampler, Use a third op amp to add the DC value to the sine wave.

Answer 2

Well, you're not telling us how you imagined it or what the traces are on your simulator so ...

Assuming

• Red is original signal.
• Blue is sample.
• Green is summing amp.

I guess you're expecting the green to oscillate symmetrically about the blue. The problem is that OA1 is a non-inverting summing amplifier which averages the two signals.

I think you need to use an inverting summing amplifier.

^{simulate this circuit – Schematic created using CircuitLab}

Figure 1. Inverting summing amplifier with virtual earth input.

I actually haven't figured out how to run the simulator yet. See if this works.

Answer 3

I think in parallel with the switch you should put a large (10k?) resistor, and an equally sized resistor between the node at C1 and SW1 and the + terminal of the op amp.

Get rid of R2 completely.

^{simulate this circuit – Schematic created using CircuitLab}