On my design, a TO228 mosfet will conduct much power. Under it, I put two Fills (one on top and one on bottom layer). I plan to link them with vias in order to conduct better power and to user the bottom one for thermal dissipation.

With altium, I added a via stitching on these fills. I also checked the option "Allow vias under SMD pads" in design rules.

The issue is that stiching is not applyed when under the pad of the mosfet. The option "allow vias under SMD" does not seem to affect via stitching.

I saw on other components design that those vias are added in the component own design.

I would preferably add the vias if I assume it is needed and only. I mean at board design time. Is there a way to ?


2d view

3d view

  • \$\begingroup\$ Have you set the minimum via-pad clearance to zero? There might be a better way that could detect different-net vias that are too close to pads, of course. \$\endgroup\$ Jan 15, 2016 at 13:48
  • \$\begingroup\$ Yes, if I change this value, the stitching moves closer or not depending on the value but it still not overlap the pad. \$\endgroup\$
    – Julien
    Jan 15, 2016 at 14:18
  • \$\begingroup\$ Will it go negative? The version we're using doesn't have via stitching (the devil we know..). \$\endgroup\$ Jan 15, 2016 at 14:51
  • \$\begingroup\$ Hum, nice try but same result. \$\endgroup\$
    – Julien
    Jan 15, 2016 at 15:34
  • \$\begingroup\$ Don't use via stitching. Just manually place the vias. My experience with automatic via stitching is that it's not very helpful. \$\endgroup\$
    – The Photon
    Jan 15, 2016 at 16:16

2 Answers 2


I'm going to agree with Photon and say you should be placing thermal vias manually, and also add that I believe they should be part of the footprint rather than added later.

Unless they've fixed it in your version, you should refer to this useful answer from @ConnorWolf which illustrates the Ctrl-H workaround for getting the vias in the pads without errors.

  • 1
    \$\begingroup\$ Adding thermal vias to the footprint library presupposes the thermal requirements and fabrication technique at that time. Adding them as part of the remainder of the thermal routing process results in an efficient design. Using via stitching, if it worked, would allow this to be quick and look nice. \$\endgroup\$
    – brainfog
    Oct 3, 2018 at 19:16

I would preferably add the vias if I assume it is needed and only. I mean at board design time. Is there a way to ?

There is nothing stopping you placing a row of vias manually and then copy/pasteing that row to produce a grid.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.