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I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the imported netlist.

  • According to the Vivado Constraint Guide, Vivado does not apply xdc constraints (Xilinx design constraints) to netlists. This feature will be implemented in the future.

  • Setting an xcf constraint file (XST constraint file), while synthesizing the netlist with XST does not help. The xcf is read and processed, but is seems that Vivado does not apply annotated/embedded constraints from ngc files.

  • Storing a ncf files (netlist constraint file) besides the ngc file does not help, because Vivado does not parse ucf style constraint files. (ISE reads ncf files and applies them to netlists, if the have the same name and location as the ngc files.)

  • I cannot synthesize the netlist with Vivido because there are bugs in Vivado, which prevent me from changing the tool chain.

How can I apply the required timing constrains?


Notes:

  • I can open the inner netlist in Vivado and see its hierarchy.
  • I can rerun XST synthesis to recreate the ngc netlist.
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  • \$\begingroup\$ Just out of curiocity, if you have access to the HDL code, and can rerun the XST, why don't you just add the files into your Vivado project? \$\endgroup\$ – FarhadA Jan 18 '16 at 9:14
  • \$\begingroup\$ The problem is that Vivado does not compile the source code due to a lack of VHDL-93 support and an intetnal memory leek when compiling this code ... \$\endgroup\$ – Paebbels Jan 18 '16 at 10:15
  • \$\begingroup\$ I am surprised, because I thought Vivado 2015.x supports VHDL-2008 so VHDL-93 should not be any problem. \$\endgroup\$ – FarhadA Jan 18 '16 at 10:32
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    \$\begingroup\$ It just supports a few features of VHDL-2008, while missing already implemented features of ISE. Moreover these features are not fully supported by xSim (the 'new' Vivado simulator ). Even if we rewrite the code to work around the usage of physical types, there is still the memory leak... \$\endgroup\$ – Paebbels Jan 18 '16 at 10:42
  • \$\begingroup\$ Have you tried to ask this question on Xilin forums, this seems to be a problem highlighted in 2014 version of Vivado and was supposed to be fixed. \$\endgroup\$ – FarhadA Jan 18 '16 at 13:17
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One solution is to write an XDC file including the required constraints and attach it to the entity name of the imported netlist using the XDC file property SCOPED_TO_REF. (Attaching it to a specific instance with SCOPED_TO_CELLS should also work.)

When using the SCOPED_TO_REF property, it must be set to the original (top-level) entity named stored within the netlist. Attaching it to the entity name of the black-box does not work (*). Moreover, the XDC file must be marked as to use "only for implementation", otherwise the synthesis step complains a critical warning. The setting "only for implementation" already includes the post-synthesis timing analysis.

(*) When attaching it to the entity name of the black-box the synthesis step will be satisfied. But, it cannot attach the timing constraints to the netlist anyway.

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