I have a pre-compiled netlist (created by Xilinx ISE 14.7), which is imported into Vivado 2015.4 and used in synthesis to assemble my complete design. Vivado reports unconstrained paths for the imported netlist.
According to the Vivado Constraint Guide, Vivado does not apply xdc constraints (Xilinx design constraints) to netlists. This feature will be implemented in the future.
Setting an xcf constraint file (XST constraint file), while synthesizing the netlist with XST does not help. The xcf is read and processed, but is seems that Vivado does not apply annotated/embedded constraints from ngc files.
Storing a ncf files (netlist constraint file) besides the ngc file does not help, because Vivado does not parse ucf style constraint files. (ISE reads ncf files and applies them to netlists, if the have the same name and location as the ngc files.)
I cannot synthesize the netlist with Vivido because there are bugs in Vivado, which prevent me from changing the tool chain.
How can I apply the required timing constrains?
- I can open the inner netlist in Vivado and see its hierarchy.
- I can rerun XST synthesis to recreate the ngc netlist.