This is a pretty general question, and some of the other answers are right. But I'd like to drill down into what is really going on here. Just for more context.
Firstly, you have to be careful, there are different transistor constructions. So in a HexFET (used in power applications and are only ever single transistors in a package) the process ties the S/D together, the structure is asymmetrical and optimized for high current. In an IC process that uses DMOS (Extended Drain - for High Voltage withstand) then you are also forced to have the Source tied to the rail.
However, in IC processes when laying out the transistors you have gate structures and S/D structures (literally Source/Drain) because in an ideal process, the Source and Drain are inter-changable.
The connection of the Bulk is what defines which of the two terminals is the source.
-> this is the key point.
For example, if you where using a SOI (Silicon On Insulator) process, that had 4 terminal transistors (not FD - Fully depleted) then you could only really talk about the two terminals of the transistors as being S/Ds.
In bulk processes, all DSM (Deep Sub-micron) processes use P-type wafers (many reason for this, but essentially P-type wafers can be manufactured, N-type are harder). That means that the P-Well for the NMOS transistor is connected to ground, well it is the ground. Even in this case, sometimes, the source is held off of ground for a desired effect. This increases Source leakage, but sometimes it is worth it.
The draw back to this structure is that the NMOS have their performance limited. Simply look at a simple source follower implemented in PMOS and in NMOS (picture of NMOS below). In a PMOS implementation, the NWell is reverse biased in the Substrate (which is p-type) and can float. A PMOS source follower can have a gain of 1.0 if wired properly.
Looking at a NMOS source follower:
Picture snipped from (1)
The bottom Vb is simply a current source for amplifier biasing, active load. You can see that M1 has it's bulk tied to ground. That means that M1's source is floating and thus M1 suffers from the backgate effect. The net result is that this amplifier can at most achieve a gain of ~0.8X. In this drawing if you were to snip the M1 Bulk and connect it to Vo the gain would jump to ~ 1.0X.
You'll note that others mentioned that Bulk and Source where connected together to optimize the transistor. In reality that only applies to those devices on the rail. You can see that any stacked transistor will have this back-gate effect manifest itself in any transistors away from the rail.
However, this is a narrow look at things. If we were to run around and make a nice process where the backgate was available then we'd suffer a couple problems (at least). One would be that the added capacitance of the well to bulk connection would slow things down. Well spacings would have to be increased because the wells are now separate, so density would go down, and then there is the issues of additional connects to the bulk taking up space as well. So for the most part, and especially for digital devices, these effects are far far worse.
(1) Shedge, M., & Itole, M. (2013). Analysis and Design of CMOS Source Followers and Super Source Follower. ACEEE Int J on ….