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I'm trying to understand all the basic connections of a MOSFET. These questions may seem very basic but I have flipped every single textbook I own and googled every single website and never found a clear cut answer to the following questions. I would appreciate all the help I can get.

1)Why is the MOSFET source connected to bulk? Is there any specific situation where the bulk isn't connected to the source? From what I have gathered, the bulk is connected to the source to establish a stable threshold voltage. If so, could we connect the bulk of a PMOS to ground and NMOS to Vdd? What difference would it make?

2)A MOSFET can function as a diode when the gate is connected to the drain. I don't really understand the physical operation behind this. However, this does make sense mathematically, as the MOSFET will always be in saturation. The current is given by, uCox(W/2L)(Vgs-Vth)^2, which means that the current graph will be quadratic which is ALMOST but not identical as the exponential equation of that of a diode. My question is, how does the performance of a MOSFET connected diode compare to that of a PN diode?

3)Of late I have seen many Rectifier circuits in IC design use MOSFET connected diodes instead of PN diodes. Is there a specific reason for this? Wouldn't a MOSFET have a relatively large area overhead when compared to using PN diode in IC design?

Your help is very much appreciated. Thanksss!!!

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1)Why is the MOSFET source connected to bulk? Is there any specific situation where the bulk isn't connected to the source? From what I have gathered, the bulk is connected to the source to establish a stable threshold voltage. If so, could we connect the bulk of a PMOS to ground and NMOS to Vdd? What difference would it make?

The source is generally connected to the bulk to produce the lowest threshold voltage. Tying the bulk to other potentials is done from time to time to better match thresholds in gm/Id matched mosftets on IC's. Most discrete mosfets though are aiming for the lowest threshold they can get.

2)A MOSFET can function as a diode when the gate is connected to the drain. I don't really understand the physical operation behind this. However, this does make sense mathematically, as the MOSFET will always be in saturation. The current is given by, uCox(W/2L)(Vgs-Vth)^2, which means that the current graph will be quadratic which is ALMOST but not identical as the exponential equation of that of a diode. My question is, how does the performance of a MOSFET connected diode compare to that of a PN diode?

Lower DC drop generally. That's about it. And as a correction it's always in either saturation or cut off (sub-threshold, you know, when the gate/drain voltage isn't high enough)

3)Of late I have seen many Rectifier circuits in IC design use MOSFET connected diodes instead of PN diodes. Is there a specific reason for this? Wouldn't a MOSFET have a relatively large area overhead when compared to using PN diode in IC design?

Two things with this.

  1. Lower on resistance means that less power is burned off as heat.
  2. I assume you're talking about an active device that purposefully measures when to conduct for each cycle. After all, if you tie a mosfet into diode, they will work in reverse.
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  • \$\begingroup\$ Thanks for your input @Dave .. What I still don't get is why a MOSFET would have a lower DC drop than a diode. Would you mind elaborating? Thanks again! :) \$\endgroup\$ – Bean Nakamura Jan 17 '16 at 0:46
  • \$\begingroup\$ Diode drop is about 0.7V, at almost all currents we care about. Mosfet drop is "linear" (roughly, with low current variation) because they have a DC on-resistance. For nmos, this is generally on the order of 0.01 -> 9 ohms. So lets think about a mosfet with a 0.01 ohm on resistance. At 10 amps, the voltage drop is only 0.1V, where as on the diode it's still 0.7V. Oh, and that diode would be MASSIVE (safely dissipate 7W). Where as the mosfet could be quite small, comparatively (only dissipating 1W). \$\endgroup\$ – Dave Jan 17 '16 at 12:43
  • \$\begingroup\$ Thanks for clarifying this @Dave ! Really appreciate it! It all makes sense to me now. :) \$\endgroup\$ – Bean Nakamura Jan 17 '16 at 13:25
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1)Why is the MOSFET source connected to bulk? Is there any specific situation where the bulk isn't connected to the source? From what I have gathered, the bulk is connected to the source to establish a stable threshold voltage. If so, could we connect the bulk of a PMOS to ground and NMOS to Vdd? What difference would it make?

The threshold voltage of the MOSFET is related to Vsb. This is called the back-gate effect:

The body effect refers to the changes in the threshold voltage by the change in V_{SB}, the source-bulk voltage. Because the body influences the threshold voltage (when it is not tied to the source), it can be thought of as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".

Back-gate effect Vth formula

Source: https://en.wikipedia.org/wiki/Threshold_voltage

Secondly, in linear operation, when the source is connected to bulk, you don't have to deal with the "transconductance" due to Vbs (gmb) since Vbs = 0. MOSFET small signal model

Image source: http://people.seas.harvard.edu/~jones/es154/lectures/lecture_4/mosfet/mos_models/mos_body_pic_2.jpg

However, it may not always be possible to have the bulk not tied to the source in a CMOS process.

2)A MOSFET can function as a diode when the gate is connected to the drain. I don't really understand the physical operation behind this. However, this does make sense mathematically, as the MOSFET will always be in saturation. The current is given by, uCox(W/2L)(Vgs-Vth)^2, which means that the current graph will be quadratic which is ALMOST but not identical as the exponential equation of that of a diode. My question is, how does the performance of a MOSFET connected diode compare to that of a PN diode?

The MOSFET is called diode-connected even though the IDS-vs-Vgs characteristic is square (saturation) instead of exponential. The reason it is diode-connected is due to the fact that it is blocking (cutoff) in the reverse direction and is not bocking in the forward direction (where it has square characteristic instead of exponential).

3)Of late I have seen many Rectifier circuits in IC design use MOSFET connected diodes instead of PN diodes. Is there a specific reason for this? Wouldn't a MOSFET have a relatively large area overhead when compared to using PN diode in IC design?

I assume this might have to do with a MOSFET connected diode enabling the control of the forward voltage. I'm not entirely sure on this though.

There is another configuration (synchronous rectification: https://en.wikipedia.org/wiki/Active_rectification) which allows for improved efficiency (high efficiency with FETs due to lower "forward voltage" leading to lower conduction losses).

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  • \$\begingroup\$ Thanks for your input @Tahmid ! Would you mind elaborating on why MOSFETs have a lower forward voltage than diodes? Thanks again! :) \$\endgroup\$ – Bean Nakamura Jan 17 '16 at 0:47
  • \$\begingroup\$ A synchronous rectifier would be actively controlled to keep it when when it is to be "forward biased" and off when it is to be blocking. The MOSFET operates in the deep triode region (deep linear region) where it can be viewed as a resistor (Rdson) when on. The "forward voltage" of this rectifier is then I*Rdson. eg When using a MOSFET, a 10mΩ Rdson is common for medium size power MOSFETs. Thus, in a situation where I=10A, forward drop of the MOSFET = 10V*10mΩ = 100mV. When using a diode, you're looking at a minimum of 300mV for a Schottky. \$\endgroup\$ – Tahmid Jan 17 '16 at 7:26
  • \$\begingroup\$ That totally makes sense! Thanks @Tahmid ! Really appreciate it! \$\endgroup\$ – Bean Nakamura Jan 17 '16 at 7:47
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The Source and Bulk do not have to be connected.

In power devices, and especially in discrete transistors, the S & B are built very close together and shorted. This improves the breakdown voltage performance of the transistor.

In an IC, in some CMOS processes, the B of NMOS devices is always substrate (ground), and so in structures such as NOR gates which have 2 NMOS in series, the 2nd NMOS doesn't have the S=B.

Generally performance (gm, current) is better with S=B, but some technologies don't allow the B to be separated from the substrate for NMOS devices. PMOS devices in an IC generally can have separate S & B connections.

If you connected the B of PMOS to GND, you would have a parasitic diode from S to B (GND), and so your supply would be shorted (unless you wanted to run on a very low supply voltage of << 0.6 V). Some very low voltage circuits do use this technique.

A MOSFET connected as a diode will generally have worse performance than a PN junction in terms of the 'sharpness' of the curve. However, FETs with low threshold voltage (say 0.4 V or lower) will turn on at a lower voltage than a diode will, and this can be useful in low voltage circuits. For the same reason that the B is always substrate in some CMOS ICs, there isn't the flexibility to use a PN junction as a diode in all circuit configurations. If the PN junction of a PMOS is used (P = Source, N = Bulk), then there are some additional parasitics that need to be considered that make this not useful generally.

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  • \$\begingroup\$ Thanks for the insight @jp314 .. I really appreciate it! :) \$\endgroup\$ – Bean Nakamura Jan 16 '16 at 16:03
  • \$\begingroup\$ Btw is there a good book or article that talks about this in depth that you happen to know of @jp314 ? All my college textbooks sadly don't have this information. :'( \$\endgroup\$ – Bean Nakamura Jan 16 '16 at 16:10
  • \$\begingroup\$ We've used Razavi's "Design of Analog CMOS Integrated Circuits" which I thought did a very good job. amazon.com/Design-Analog-CMOS-Integrated-Circuits/dp/0072380322 \$\endgroup\$ – Tahmid Jan 16 '16 at 16:51
  • \$\begingroup\$ @jp314 Why wouldn't S=B in the second transistor in a CMOS NOR gate? Specifically, which transistor in the linked answer with a NOR gate does not connect Source to Body? electronics.stackexchange.com/a/110673/95675 \$\endgroup\$ – cr1901 May 11 '18 at 2:19
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There is one part of your question that I can be a little more thorough with:

Is there any specific situation where the bulk isn't connected to the source?

There are at least two classes of device where this is true:

Analogue switches

In a CMOS switch, body diode conduction is an undesirable feature (the switch would always conduct), so the basic connections are this:

CMOS Switch

Note that the substrate is tied to the supplies such that the body diodes will not conduct provided the analogue input / output does not exceed the supplies.

There is an excellent application note on these devices.

There are also some high side switches that expose the substrate.

It was not uncommon some years ago (20 or so) for 4 terminal devices to be widely available (there were some niche uses particularly in sample and hold applications where an exposed substrate was advantageous)

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This is a pretty general question, and some of the other answers are right. But I'd like to drill down into what is really going on here. Just for more context.

Firstly, you have to be careful, there are different transistor constructions. So in a HexFET (used in power applications and are only ever single transistors in a package) the process ties the S/D together, the structure is asymmetrical and optimized for high current. In an IC process that uses DMOS (Extended Drain - for High Voltage withstand) then you are also forced to have the Source tied to the rail.

However, in IC processes when laying out the transistors you have gate structures and S/D structures (literally Source/Drain) because in an ideal process, the Source and Drain are inter-changable.

The connection of the Bulk is what defines which of the two terminals is the source.

-> this is the key point.

For example, if you where using a SOI (Silicon On Insulator) process, that had 4 terminal transistors (not FD - Fully depleted) then you could only really talk about the two terminals of the transistors as being S/Ds.

In bulk processes, all DSM (Deep Sub-micron) processes use P-type wafers (many reason for this, but essentially P-type wafers can be manufactured, N-type are harder). That means that the P-Well for the NMOS transistor is connected to ground, well it is the ground. Even in this case, sometimes, the source is held off of ground for a desired effect. This increases Source leakage, but sometimes it is worth it.

The draw back to this structure is that the NMOS have their performance limited. Simply look at a simple source follower implemented in PMOS and in NMOS (picture of NMOS below). In a PMOS implementation, the NWell is reverse biased in the Substrate (which is p-type) and can float. A PMOS source follower can have a gain of 1.0 if wired properly.

Looking at a NMOS source follower: enter image description here

Picture snipped from (1)

The bottom Vb is simply a current source for amplifier biasing, active load. You can see that M1 has it's bulk tied to ground. That means that M1's source is floating and thus M1 suffers from the backgate effect. The net result is that this amplifier can at most achieve a gain of ~0.8X. In this drawing if you were to snip the M1 Bulk and connect it to Vo the gain would jump to ~ 1.0X.

You'll note that others mentioned that Bulk and Source where connected together to optimize the transistor. In reality that only applies to those devices on the rail. You can see that any stacked transistor will have this back-gate effect manifest itself in any transistors away from the rail.

However, this is a narrow look at things. If we were to run around and make a nice process where the backgate was available then we'd suffer a couple problems (at least). One would be that the added capacitance of the well to bulk connection would slow things down. Well spacings would have to be increased because the wells are now separate, so density would go down, and then there is the issues of additional connects to the bulk taking up space as well. So for the most part, and especially for digital devices, these effects are far far worse.

(1) Shedge, M., & Itole, M. (2013). Analysis and Design of CMOS Source Followers and Super Source Follower. ACEEE Int J on ….

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