Sorry for the Terrible Diagram

I was hoping to use a Linear Comparator with a latch such as LT1016 as a trigger for the Register output clock for a 74HC590.

The 74HC590 is going to be cascaded with it's RCO going to several more 74HC590's on the 590's counter clock I am going to find (hopefully) an adjustable clock source so I can count the Time it takes between when a UltraSonic Transducer to receive a signal so I can calculate the velocity of the air in between them.

I was hoping to connect the comparator's output to it's Latch so I only catch the first pulse as I'm assuming their is going to be echos and whatnot after it first goes off.

Is a Linear Comparator the right tool for this situation? I've seen other's that use a series of OPAMPS amplify the transducer's reception to something logic level (And I've ordered some as well to try) but this seems like a more straight forward way then trying to figure out the gain needed and the noise and whatnot, and with OPAMPS I'm going to need to figure out a way to stop them to keep the Register on the 590 from updating.


1 Answer 1


The concept looks ok, but as always, the devil is in the details. I have used this particular device in a capture scenario (for timing analogue signal events into the digital domain) and there is no reason it cannot be successful if you take care.

You will need to do at least some input signal conditioning to ensure the signal fed to the (very fast) LT1016 is within it's input common mode range as the datasheet highlights numerous ways in which a measurement can go wrong (page 6 of the datasheet onwards).

Input signal conditioning will also be necessary to ensure that the latch pin setup and hold times are not violated; the input may need to be stretched a bit if the pulse you see is extremely fast.

The datasheet has this to say:

LATCH Pin Dynamics

The LATCH pin is intended to retain input data (output latched) when the LATCH pin goes high. This pin will float to a high state when disconnected, so a flowthrough condition requires that the LATCH pin be grounded. To guarantee data retention, the input signal must be valid at least 5ns before the latch goes high (setup time) and must remain valid at least 3ns after the latch goes high (hold time). When the latch goes low, new data will appear at the output in approximately 8ns to 10ns. The LATCH pin is designed to be driven with TTL or CMOS gates. It has no built-in hysteresis.

The applications section (see Figure 14) suggests that the output should be buffered by gates, a good idea which will help in ensuring at least the latch pin setup time (due to gate propagation delay) can be achieved.

Pay great attention to the cautions in the applications section if you intend to use this specific part as it is not suitable for breadboarding with wires.

All that said, this is perfectly do-able, but some details of your expected signal at the receiving transducer would be helpful.

In my application, I used a separate latch on the output as I could not guarantee the setup / hold time requirements.

If you use a different part that has slow output rise / fall times, you should buffer the output via a schmitt trigger device such as the 74HC14 to ensure that you do not violate the maximum input rise and fall times of the 74HC5690.


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