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For NAND, I am doing a truth table for it and then truth tables for all the possible combinations, but as you can see the process is very long and I am still yet to get an answer. Same goes for NOR gate. Any help is appreciated. (Answer welcome :P)

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As equations.

\$\overline{ABC} = \overline{(AB)C} = \overline{\overline{\bar A+\bar B}\cdot C}\$

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  • \$\begingroup\$ Wow that's cool \$\endgroup\$ – studious Jan 16 '16 at 21:58
  • \$\begingroup\$ It's also something that should have been covered in Boolean Algebra 101. \$\endgroup\$ – Ignacio Vazquez-Abrams Jan 16 '16 at 21:59
  • \$\begingroup\$ First week of the semester and so on \$\endgroup\$ – studious Jan 16 '16 at 22:00
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    \$\begingroup\$ Though to build that from NAND/NOR gates would take four gates in total. It can be done with just three gates. Notice that the \$(AB)\$ is a 2-input AND gate, which is equivalent to \$\overline{\overline{AB}}\$ which is a 2-in NAND gate followed by an inverter (another 2-in NAND with both inputs tied together). So \$\overline{ABC} = \overline{\overline{\overline{A \cdot B}}\cdot C}\$ \$\endgroup\$ – Tom Carpenter Jan 17 '16 at 3:53
  • \$\begingroup\$ Is there any other way to do this other than this? \$\endgroup\$ – studious Jan 18 '16 at 14:02
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An alternate approach is given.

schematic

simulate this circuit – Schematic created using CircuitLab

The schematic represents the function: $$Y = \overline{ABC} = \overline{\overline{\overline{AB}} C}$$

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  • \$\begingroup\$ How did you find Step 2 from Step 1? \$\endgroup\$ – studious Jan 18 '16 at 14:02
  • \$\begingroup\$ @studious \$Y=\mathtt{nand(A,B,C)} = \mathtt{not\{and(A,B,C)\} = \\ not\{and(and(A,B),C)\}=nand\{and(A,B),C\}}\$ \$\endgroup\$ – nidhin Jan 18 '16 at 16:34
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Note that in the above answers, there are three propagation delays for A and B, but only one for C. Therefore, if propagation delays matter, put two nand gates in series in line C, wired as inverters.

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