Yes this can be easily by considering the following picture
- Here in the above diagram,this D flipflop works when rising edge of clock is detected.On power ON the D will be in OFF and hence Q also OFF.As told early,the flipflop activates when +ve edge is detected.When rising edge is detected,the flipflop gets actives and inverted Q(LOW) and Q(HIGH) at this instant.This inverted Q is fed back to the D at the same instant
- The output of the flipflop never change until positive edge is detected.The next raising clock will happens at the next cycle of the clock signal.Unless,the output never changes
- Now the next rising edge is detected,The inverted Q goes HIGH and Q goes to LOW.This inverted Q is fed to D again and wait until the rising edge
- This cycle continuous.From the diagram,you can observe that,for a complete cycle of CLK,one half of clock is get at the output of D flipflop.Thus,the input CLK is divided into 2 when it appears at the output of the Q.
- The circuit in the diagram is not similar with your circuit.I just mad a JK flipflop ad D flipflop.Consider the clock and understand based on explanation.
A circuit that toggles the output for the rising edge of input is a frequency divide-by-2 system. JK flipflop in toggle mode (J=K=1) and T flipflop (with T=1) can readily implement this circuit. But all we have is a DFF.
A positive edge triggered DFF captures the input(Data input) at rising edge of clock and this captured value is given as output. So if we connect inverted version of output of DFF as the data input to the DFF, the output will toggle for every rising edge of clock. This circuit will divide the clock frequency by 2.