I am using a Xilinx 7-Series GTXE2 Transceiver configured as SATA host PHY. This transceiver is interfacing with an SATA Host controller and an SATA Gen1 device.
During initialization, I am able to see COMRESET, COMINIT and COMWAKE from host and device. They have been captured on RXDATA/TXDATA. TX/RXELECIDLE are de-asserted correctly. The host controller is able to receive and response to complete OOB sequence.
After that, the host is sending
D10.2 at 1.5 Gbps to start speed negotiation. The device is responding with \$ALIGN_p\$ primitives, which are send at 1.5 Gbps.
However, from RXDATA, I can only see
D27.3 D10.2 D10.2 K28.5 symbols appearing for only one clock cycle, which is 20'haaaaa, follow by 20'h5f0e4. After that, I am seeing 20'h55555, follow by 20'h5f0e4. The
K28.5 character appeared to be correct.
D10.2 appeared to be either swapped or shifted. Because the GTXE2 transceiver is unable to decode \$ALIGN_p\$, the speed negotiation failed.
I have set
RXCDR_CFG to (72'h0380008BFF40100008). The FPGA is connected to a Gen1 device.
I have implemented a control signal to release
RXCDRHOLD when I find 20'haaaaa follow by 20'h5f0e4 in the data stream. After I release the
hold signal, it becomes 20'h55555 and 20'h5f0e4. If I don't release
RXCDRHOLD, I see garbage on
RXDATA. So it seems that releasing
RXCDRHOLD only improve part of the \$ALIGN_p\$ characters.
D27.3 was right.
D10.2 is bit swapped or shifted.
I have came across another post, wherein the author may have experienced similar problems. He modified
RXCDR_CFG: Configuring a 7-Series GTXE2 transceiver for Serial-ATA (Gen1/2/3)
I was wondering, if anyone has experienced this problem with Xilinx 7-Series GTXE2 transceivers.