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Under the following tutorial:

http://www.allaboutcircuits.com/textbook/semiconductors/chpt-4/biasing-techniques-bjt/

They explain push pull operation. But should't negative terminal be separate with the ground? Dont we need +Vcc and -Vcc

Here is the push-pull from the tutorial:

http://sub.allaboutcircuits.com/images/03126.png

EDIT: here is my simulation:

enter image description here

Green is input, red is output.

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    \$\begingroup\$ One of your transistors is upside down. And there's no base bias network. \$\endgroup\$
    – user16324
    Commented Jan 19, 2016 at 15:06

2 Answers 2

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But should't negative terminal be separate with the ground? Dont we need +Vcc and -Vcc

No, that would work providing the load is connected via an output coupling capacitor: -

enter image description here

Here's another: -

enter image description here

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  • \$\begingroup\$ ? Because I simulated without a cap and the result was a rectified sinusoid \$\endgroup\$
    – user16307
    Commented Jan 19, 2016 at 14:30
  • \$\begingroup\$ Yeah that might happen! \$\endgroup\$
    – Andy aka
    Commented Jan 19, 2016 at 14:31
  • \$\begingroup\$ i edited my question. adding a cap didnt work for me. please see my schematics. just a cap is not enough? \$\endgroup\$
    – user16307
    Commented Jan 19, 2016 at 14:38
  • \$\begingroup\$ oh is that because mine is not biased?? \$\endgroup\$
    – user16307
    Commented Jan 19, 2016 at 14:43
  • \$\begingroup\$ Q2 is the wrong way round too. Yes, the transistors need decent biasing. \$\endgroup\$
    – Andy aka
    Commented Jan 19, 2016 at 14:43
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Your output doesn't seem to have any (noticeable) DC offset so you can leave out the output capacitor for simulation sake.

You don't get a negative swing because the output is clipped between 0 and +Vcc. You can do one of two things to fix this:

  1. Add a DC offset to your input signal and add output capacitor.
  2. Add a negative supply equal to -(+Vcc).

Also, you would want to add a Vbias between the output stage inputs equal to 2*Vbe to keep both transistors at the verge of saturation.

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