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I was looking at a DDR2 design that had it's ODT pin pulled low, presumably this was done because the CPU doesn't have and ODT pin. Reading the datasheet though I don't see a clear explanation of what that does. I'm thinking it disables ODT? Anyone know?

I was also wondering what the consequences of pulling it high and enabling it all the time would be. I feel like that should be OK, just maybe consumes more power than it needs to and doesn't do much on for a read.

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The on-die termination is controlled by some register settings (EMR) and pulling the ODT pin high. Basically, the ODT pin is pulled high during certain DRAM access. Looking at page 127 for ODT timing should give you a better idea on how that pin is used.

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  • \$\begingroup\$ I understand how it is used when you have a controller that supports it. In this design the pin is only pulled low and connected to nothing else. I was trying to understand the effect that would have. Is ODT then always disabled. \$\endgroup\$
    – confused
    Commented Jan 19, 2016 at 18:50
  • \$\begingroup\$ Yes, if it is held low then it would be always disabled \$\endgroup\$
    – cimarron
    Commented Jan 19, 2016 at 19:14

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