in -> circuit1 -> circuit2 -> out
in -> circuit2 -> circuit3 -> out
Is there a way to 'tell' this to vivado so that the timing and implementation will take this in to account when determining if I meet the timing constraints?
I assume this will be done by 'setting false path'. But I'm not sure how exactly choose 'trough' what this path goes, since after synthethisation vivado 'joins' these entities (I'm using the 'rebuilt' setting during synthesis).
I have the circuits in separate entities, so I'm wondering if there is a way to use the 'set false path -trough' constraint with vhdl design entities.