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I've been researching booting and flash memory as found in embedded devices like smartphones, tablets, and boards. There are numerous schemes and an equally numerous amount of obscure terminology. I understand NOR flash allows for XIP. Some NAND chips seem to have special "boot areas" or "boot partitions", and even "boot modes" (though that only makes sense in the context of processors to me).

Setups can utilize boot ROMs embedded in application processors, have separate chips for boot code (on NOR) and system code (on NAND), use U-Boot stored on the internal memory chip as an IPL, or use eMMCs that are boot code-aware with configurable ranges for "boot areas".

Are there memory chips that have a NOR portion and a NAND portion combined into a single address space. That way, say, addresses 0x00000000 through 0x0000FFFF contain a bootloader that can execute in place while addresses 0x00010000 through 0xFFFFFFFF correspond to NAND flash?

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  • \$\begingroup\$ NOR and NAND refer to the structure of the memory cell. the other features are not dependant on memory cell structure, you request for parts is off topic. \$\endgroup\$ – Jasen Jan 21 '16 at 2:51
  • \$\begingroup\$ @Jasen Not a request for parts. I'm asking if such a scheme is used. \$\endgroup\$ – Melab Jan 21 '16 at 6:03
  • \$\begingroup\$ I don't think NAND and NOR processes are compatible. So you would not find them together on the same die. \$\endgroup\$ – mkeith Jan 21 '16 at 8:11
  • \$\begingroup\$ Also, NOR is huge, in terms of die area. So it would not make sense to combine them. \$\endgroup\$ – mkeith Jan 21 '16 at 8:12
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I'm not aware of a chip that combines the two onto a single die like that, or a shared address space but I'm sure someone has made a multi-chip module with both topologies on-board.

To address your comment about NAND boot areas, they are special only because some NAND chips are sold with guaranteed 'good' sectors at the start, where you can store infrequently updated code such as a bootloader or other IPL. This saves you from having to juggle that critical piece of software around during normal NAND controller operations that may re-map bad blocks, etc.

I suppose someone who implemented their own memory controller in a FPGA and connected two separate parallel memories, one NAND and one NOR could implement such a device, but that's a lot of hardware.

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  • \$\begingroup\$ As the NAND chips move to smaller process nodes, this system of having good boot sectors is going out the window. Best to use some form of error correction in your bootloader code, or store it on some type of NOR. \$\endgroup\$ – mkeith Jan 21 '16 at 8:10

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